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**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86
***Info:
The CS8231 TURBO CACHE BASED 386/AT CHIPSet is a seven chip VLSI
implementation of most of the system logic to implement a CACHE BASED
iAPX 386 based system. The CHIPSet is designed to offer a 100% PC AT
compatible integrated solution. The flexible architecture of the
CHIPSet allows it to be used in any iAPX386 based system design, such
as CAD/CAE workstations, office systems, industrial and financial
transaction systems.
The CS8231 CHIPSet combined with CHIP's 82C206, Integrated Peripherals
Controller, provides a complete PC AT compatible system using only 40
components plus memory devices.
The CS8231 CHIPSet consists of one 82C301 Bus Controller, one 82C307
Integrated CACHE/DRAM controller, one each of 82A303 and 82A304
Address Bus Interfaces, two 82B305 Data Bus Interfaces, and a 82A306
Control Signal Buffer.
The CHIPSet supports a local CPU bus, a 32-bit system memory bus, and
AT buses as shown in the system diagram below. The 82C301 and 82A306
provide the generation and synchronization of control signals for all
buses. The 82C301 also supports an independent AT bus clock, and
allows for dynamic selection of the processor clock between the 16M
Hz, 20MHz, or 25MHz clocks and the AT bus clock. The 82A306 provides
buffers for bus control signals in addition to other miscellaneous
logic functions.
The 82C307 is a high performance and high integration CACHE/DRAM
controller designed to interface directly to the 80386 micro-
processor. It maintains frequently accessed code and data in high
speed memory, allowing the 80386 to operate at its maximum rated freq-
uency with near zero waitstates. By integrating DRAM control func-
tions on-chip, it supports simultaneous activation of cache and DRAM
access, thereby minimizing the cache miss cycle penalty. It has
hardware support to allow the user to designate up to four blocks (of
variable size from 2KB to 128KB) of main memory as non-cacheable
address space. This feature is important for compatibility issues
when operating in a multiprocessing or LAN environment, or where dual-
port memory is used, and to designate certain regions of video RAM as
non-cacheable. This feature eliminates the need to use very fast PALs
externally to decode non-cacheable regions and gives the user much
more flexibility. Optional EDC support logic is integrated on to the
82C307 which allows it to interface to any of the generically
available 32-bit Error Detection and Correction Circuits to realize a
highly reliable memory subsystem.
Cache coherency is maintained during DMA cycles by channeling all acc-
esses through the cache controller logic. During DMA read operations,
the cache RAM is not accessed and data is retrieved from the main
memory. During DMA write operations, if a cache hit is detected, the
cache RAM is updated and the corresponding tag validated. Cache
coherency is maintained at all times, with no performance penalty.
The 82C307 is available in a 100 pin PFP package.
The 82A303 and 32A304 interface between all address buses, and the
addresses needed for proper data path conversion. Two 828305 are used
to interface between the local, system memory, and at data buses. In
addition to having high current drive, they also perform the
conversion necessary between the different sized data paths.
***Configurations:...
***Features:...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:
F64300 Wingine DGX 2MB, (appears to be a VLB version adapted from the proprietary 64200)
F64310 Wingine DGX 2MB (appears to be a PCI version adapted from the proprietary 64200)
OC65540 VGA BIOS c:95
OC65545 VGA BIOS same as 540 but has hardware overlay feature.
94C2001 PUMA (Programmable Universal Micro Accelerator) 50MHz Video accelerator
82C840 8514/A clone
82C9001A Video controller
82C404 Programmable clock synthesizer
82C402 VGA clock Synthesizer
82C411 Flat panel color pallet/DAC
82C425 82C425 CGA, CRT+LCD support, greyscale on LCD, supports two softfonts (up to 8x16 pixels) allowing 512 characters on screen, no snow
82C426 82C426 CGA, CRT, color LCD+AT&T400 support, max 32KB RAM
82C450 82C450 1MB VRAM, max 800x600 256color
82C451 82C451 VGA 256KB DRAM, max 800x600 16color c:90
82C452 82C452 1MB DRAM, max 640x480 256color, 1024x768 16color
82C453 82C453 1MB DRAM, max 800x600 256color
82C455 82C455 256KB DRAM Flat Panel version
82C456, 456A 82C456 256KB DRAM Flat Panel/CRT
82C457 82C457 Full color
82C45x series are VGA
'The 655xx series chips are SVGA video controller chips for flat panel
displays and CRTs. They also provide some level of CGA, MDA, EGA, and
Hercules compatibility, and various accelerator features. They are
designed with various features for reducing power consumption and
optimizing display quality.
source:http://www.igl.ku.dk/~fsp/varia/ct5xx.html
see the above source for more details.
82C481 True-Color Graphics Accelerator Wingine?
F65510 65510 LCD / CRT
F65520 65520 1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color
F65525 65525 LCD / CRT
F65530 65530 1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color, VLB
F65535 65535 LCD / CRT
F65540 65540 same as 65545 but without BitBLT and hw cursor
F65545 65545 mobile, 512-1024KB DRAM, ISA / PCI / VLB
65546 65546
F65548 65548
F65550 65550 HighQV32, mobile, 1-2MB DRAM, PCI / VLB
B65554 65554 HighQV64, mobile, 1-4MB DRAM, BGA
F65555 65555 HighQVPro, mobile, 1-4MB EDO, BGA
F68554 68554 HiQVision
F68555 68555
F69000 69000
M69000 69000 HighQVideo, mobile, 83MHz RAM, 2MB SDRAM on die, PCI / AGPx1, 135MHz RAMDAC, BGA, MiniBGA
F69030 69030 HighQVideo, mobile, 100MHz RAM, 4MB SDRAM on die, PCI / AGPx1, 170MHz RAMDAC, BGA, MiniBGA
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:...
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
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