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*_IBM...
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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**Video:
F64300 	Wingine DGX 2MB, (appears to be a VLB version adapted from the proprietary 64200)
F64310 	Wingine DGX 2MB  (appears to be a PCI version adapted from the proprietary 64200)

OC65540   VGA BIOS  c:95
OC65545   VGA BIOS same as 540 but has hardware overlay feature.

94C2001   PUMA (Programmable Universal Micro Accelerator) 50MHz Video accelerator

82C840 	  8514/A clone
82C9001A  Video controller

82C404          Programmable clock synthesizer
82C402 	  	VGA clock Synthesizer
82C411          Flat panel color pallet/DAC

82C425 	  	82C425 	CGA, CRT+LCD support, greyscale on LCD, supports two softfonts (up to 8x16 pixels) allowing 512 characters on screen, no snow
82C426 	  	82C426 	CGA, CRT, color LCD+AT&T400 support, max 32KB RAM
82C450 	  	82C450 	1MB VRAM, max 800x600 256color
82C451 	  	82C451 	VGA 256KB DRAM, max 800x600 16color c:90
82C452 	  	82C452 	1MB DRAM, max 640x480 256color, 1024x768 16color
82C453 	  	82C453 	1MB DRAM, max 800x600 256color
82C455 	  	82C455 	256KB DRAM Flat Panel version
82C456, 456A  	82C456 	256KB DRAM Flat Panel/CRT
82C457 	  	82C457 	Full color

82C45x series are VGA

'The 655xx series chips are SVGA video controller chips for flat panel
displays and CRTs. They also provide  some level of CGA, MDA, EGA, and
Hercules  compatibility, and  various accelerator  features. They  are
designed  with various  features  for reducing  power consumption  and
optimizing display quality. 
source:http://www.igl.ku.dk/~fsp/varia/ct5xx.html

see the above source for more details.

82C481 True-Color Graphics Accelerator Wingine?

F65510 	65510 	LCD / CRT
F65520 	65520 	1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color
F65525 	65525 	LCD / CRT
F65530 	65530 	1MB D/VRAM, Full color, max 1280x1024 16color & 800x600 256 color, VLB
F65535 	65535 	LCD / CRT
F65540 	65540 	same as 65545 but without BitBLT and hw cursor
F65545 	65545 	mobile, 512-1024KB DRAM, ISA / PCI / VLB
65546 	  	65546 	 
F65548 	65548 	 
F65550 	65550 	HighQV32, mobile, 1-2MB DRAM, PCI / VLB
B65554 	65554 	HighQV64, mobile, 1-4MB DRAM, BGA
F65555 	65555 	HighQVPro, mobile, 1-4MB EDO, BGA
F68554 	68554 	HiQVision
F68555 	68555 	 
F69000  69000 	
M69000 	69000 	HighQVideo, mobile, 83MHz RAM, 2MB SDRAM on die, PCI / AGPx1, 135MHz RAMDAC, BGA, MiniBGA
F69030 	69030 	HighQVideo, mobile, 100MHz RAM, 4MB SDRAM on die, PCI / AGPx1, 170MHz RAMDAC, BGA, MiniBGA


*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82396SX     Smart Cache                                     12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK320        386DX Chip Set                                 c:Sep91
***Info:
The  HTK320 chip  set  is a  2-chip, high-performance,  cost-effective
solution for the 80386DX microprocessor. In its minimum configuration,
this  highly  integrated chip  set  requires  only  four external  TTL
devices to implement a fully  compatible IBM PC/AT system at speeds up
to 40 MHz.

The HTK320 is based on Headland’s Bus Architecture and consists of the
HT321-ISA Controller and the  HT322-Memory Control Unit (MCU) packaged
in  two 184-pin plastic  quad flat  packs. Among  its features  are an
on-chip cache controller and internal tag RAM.

Unlike  other  3rd  generation  chip  sets that  have  integral  Cache
Controllers,  the HTK320 integrates  the high-speed  tag RAM  into the
chip  set to  enhance performance  and significantly  reduce component
count  and  manufacturing  cost.   The  direct  mapped  or  2-way  set
associative cache  design supports external  cache sizes of  32K, 64K,
and 128K.

The  HTK320  can  support  Peripheral  Devices such  as  VGA  or  SCSI
controllers on the  local processor bus, or any  3rd party device that
is  designed to  work within  the 386DX  Bus Protocol  and  Timing. By
eliminating the ISA backplane bottleneck, system designers can greatly
improve the  performance of functions such as  graphics generation and
disk access.

The HTK320 incorporates a 4-leve1  deep Write Buffer and performs byte
gathering into  32 bit  accesses to the  DRAM.  This  facilitates real
zero  wait  state  writes  and,   when  coupled  with  the  2-way  set
associative cache, provides enhanced memory performance.

The HTK320 Supports up to 4  banks of DRAM, configurable as 1-4 Banks.
This  flexible memory architecture  allows for  any memory  type, from
256Kb to  16Mb devices,  in any bank.   Maximum system  performance is
achieved  from  the  DRAM   banks  through  various  means,  including
interleave of  Memory Bank  and/or Page, and  CAS before  RAS refresh.
The memory may also be tuned  to its maximum potential through the use
of  extensive   DRAM  timing  Control   Registers,  controls  include,
Precharge time, Access  time on Reads, Active time  on Writes, as well
as CAS  and RAS  delays.  In addition,  further system  performance is
gained  by separate  timing parameters  on the  read and  Write cycles
which  allow  system  designers  to  take  maximum  advantage  of  the
pipelined structure of the chip set.

The  HTK320 also  supports  extensive mapping  registers, which  allow
system designers to take maximum advantage of system memory.  The chip
set supports EMS LIM 4.0, allows  for mixed Shadow/Remap in 16K blocks
between the 640K and 1M boundaries, and eliminates the requirement fer
external  decoding  logic  by  support of  27  Programmable  Non-cache
regions.   With  the'  extensive  HTK320  mapping  capability,  it  is
feasible  to seamlessly  place  3rd  party devices  on  the local  bus
without  the  need  for  external  TTL  support.  The  HTK320  Mapping
structure provides  for a single 8-bit  EPROM to be used  for both the
system  and Video  BIOS, further  reducing the  system chip  count and
cost.

***Configurations:...
***Features:...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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