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**Intro:
The information contained within this file should not be considered
100% correct. Where possible information has been taken from
datasheets, however even this info may be incorrect. The datasheets
state what the chip should do, not what they actually do. This is,
compounded further by different revisions of chips.
This document will never be complete, and I have no intention of
finding every datasheet for every chip set. Some of the chip sets
listed are from later systems in the PIII/P4/Athlon era. There are
many websites with information on these chip sets and these entries
will likely not be expanded upon. The focus of this document is early
PC/XT to Pentium chip sets. There are few sites that clearly illu-
strate this information, and how they relate to each other.
I aim to prioritize cataloging significant, rare or otherwise
interesting chip sets.
BTW the reason I wrote all of this down, is so that I could FORGET it.
Basically I needed to free up some RAM. I've a head full of arcane
snippets of information on this subject. I don't want to end up a
crazy old man ranting random disjointed information ("The C&T CS8220
came before the CS8221 you KNOW!") to disinterested passersby, unable
to see how senile I've become. A side benefit, this might be useful to
someone else:-)
**Quote style:...
**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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