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*Chips & Technologies...
**82C710 Universal Peripheral Controller c:Aug90
***Info:...
***Versions:...
***Features:
o Low Power CMOS, 100pin PQFP Package
o On Chip Power Management Features, Controllable Through Hardware
and/or Software
o 100% IBM PC-XT/AT Compatibility.
o 24 mA IBM AT/XT Bus Interface Buffers
o Schmitt Trigger Input on Reset Pin
o 1 x 16450 Compatible UART
o 1 IBM PC-XT/AT Compatible Enhanced (Bi-Directional) Parallel Port
o 24 mA Parallel Port Output Drivers
o IDE Interface (For Embeded AT & XT Hard drives)
o General Purpose Chip Select
o Real Time Clock chip Select
o Fully uPD72065B and IBM-BIOS Compatible Floppy Disk Controller
- Licensed NEC design
- 48 mA floppy drive interface buffers
- Data rate and drive control registers
- Two pin programmable precompensation modes
- Supports two floppy drives directly and up to four with an
external decoder
- DMA enable logic
o On-Chip Precision Analog Data Separator
- +/-380ns at 500K bps
- +/-740ns at 250K bps
- Automatically selects one of three filters
- Supports 250 Kb/s, 300 Kb/s, 500 Kb/s & 1 Mb/s data rates
o Single 24 MHz Crystal/Oscillator for UART and Floppy Disk
Controller
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**GCK113 80386 AT Compatible Chip Set c:oct89
***Info:...
***Configurations:...
***Features:...
**GCK181 Universal PS/2 Chip Set c:Mar89...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
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