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**CS8231 TURBO CACHE-BASED 386/AT (82C301/307/303/304/305/306) c86
***Info:
The CS8231 TURBO CACHE BASED 386/AT CHIPSet is a seven chip VLSI
implementation of most of the system logic to implement a CACHE BASED
iAPX 386 based system. The CHIPSet is designed to offer a 100% PC AT
compatible integrated solution. The flexible architecture of the
CHIPSet allows it to be used in any iAPX386 based system design, such
as CAD/CAE workstations, office systems, industrial and financial
transaction systems.
The CS8231 CHIPSet combined with CHIP's 82C206, Integrated Peripherals
Controller, provides a complete PC AT compatible system using only 40
components plus memory devices.
The CS8231 CHIPSet consists of one 82C301 Bus Controller, one 82C307
Integrated CACHE/DRAM controller, one each of 82A303 and 82A304
Address Bus Interfaces, two 82B305 Data Bus Interfaces, and a 82A306
Control Signal Buffer.
The CHIPSet supports a local CPU bus, a 32-bit system memory bus, and
AT buses as shown in the system diagram below. The 82C301 and 82A306
provide the generation and synchronization of control signals for all
buses. The 82C301 also supports an independent AT bus clock, and
allows for dynamic selection of the processor clock between the 16M
Hz, 20MHz, or 25MHz clocks and the AT bus clock. The 82A306 provides
buffers for bus control signals in addition to other miscellaneous
logic functions.
The 82C307 is a high performance and high integration CACHE/DRAM
controller designed to interface directly to the 80386 micro-
processor. It maintains frequently accessed code and data in high
speed memory, allowing the 80386 to operate at its maximum rated freq-
uency with near zero waitstates. By integrating DRAM control func-
tions on-chip, it supports simultaneous activation of cache and DRAM
access, thereby minimizing the cache miss cycle penalty. It has
hardware support to allow the user to designate up to four blocks (of
variable size from 2KB to 128KB) of main memory as non-cacheable
address space. This feature is important for compatibility issues
when operating in a multiprocessing or LAN environment, or where dual-
port memory is used, and to designate certain regions of video RAM as
non-cacheable. This feature eliminates the need to use very fast PALs
externally to decode non-cacheable regions and gives the user much
more flexibility. Optional EDC support logic is integrated on to the
82C307 which allows it to interface to any of the generically
available 32-bit Error Detection and Correction Circuits to realize a
highly reliable memory subsystem.
Cache coherency is maintained during DMA cycles by channeling all acc-
esses through the cache controller logic. During DMA read operations,
the cache RAM is not accessed and data is retrieved from the main
memory. During DMA write operations, if a cache hit is detected, the
cache RAM is updated and the corresponding tag validated. Cache
coherency is maintained at all times, with no performance penalty.
The 82C307 is available in a 100 pin PFP package.
The 82A303 and 32A304 interface between all address buses, and the
addresses needed for proper data path conversion. Two 828305 are used
to interface between the local, system memory, and at data buses. In
addition to having high current drive, they also perform the
conversion necessary between the different sized data paths.
***Configurations:...
***Features:...
**CS8232 CMOS 386/AT (82C301/302/303/304/305/306) c86...
**CS8233 PEAK/386 AT (Cached) (82C311/82C315/82C316) c:Dec90...
**CS8236 386/AT (82C301/2/3/4/5/6/206) c86...
**CS8237 TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206) c86...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88
***Info:...
***Versions:...
***Features:...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90
***Info:...
***Configurations:...
***Features:...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
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