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*Chips & Technologies...
**82C601/A Single Chip Peripheral Controller <08/30/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
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*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91
***Info:...
***Configurations:...
***Features:
o 100% EISA compatible
o 20/25/33/50 MHz 80486 DX/SX CPU operation
o 25/33/40 Mhz 80386DX CPU Operation
o Integrated write back cache controller with built-in tag comparator
o Concurrent CPU-cache and EMA/master operations with bus snooping
o Only ten TTL components are required
o Complete EISA system can be built on a baby AT sized motherboard
o Flexible cache size from 64KB to 1MB
o Page mode DRAM operation supporting 1 to 4 banks up to 256MB
o Video/system BIOS, shadowing and caching
o Supports both conventional and concurrent configurations
o Inclusive secondary cache for snoop filtering
o Synchronous EISA bus clock
o Transparent Gate A20 and CPU reset
o CPU local bus device support
o Supports 80387, 80487SX and Weitek 3167/4167 co-processors
o Decoupled refresh without holding CPU
o Staggered DRAM refresh to minimize power supply noise
o Rlch set of register options to allow customization
o Three 160-pin PQFP packages in low power and high speed 0.8um CMOS
Technology
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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