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*Chips & Technologies...
**CS8232   CMOS 386/AT              (82C301/302/303/304/305/306)   c86
***Notes:...
**CS8233   PEAK/386 AT (Cached)     (82C311/82C315/82C316)     c:Dec90...
**CS8236   386/AT                   (82C301/2/3/4/5/6/206)         c86...
**CS8237   TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206)         c86...
**CS8238   CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226)   c:Aug89...
**CS82310  PEAK/DM 386 AT           (82C351/82C355/82C356)         c91...
**CS8281   NEATsx (386SX)           (82C811/812/215/206)       c:Dec89...
**CS8283   LeAPset-sx               (82C841/82C242/82C636)     c:Mar90...
**CS8285   PEAKsx                   (82C836/82C835)                c91...
**CS8288   CHIPSlite-sx             (82C836/82C641/82C835)          c?...
**CS4000   WinCHIPS                 (64200/84021/84025)            c92...
**CS4021   ISA/486                  (84021/84025)                  c92...
**CS4031   CHIPSet                  (84031/84035)              5/10/93...
**CS4041/5 CHIPSet                  (84041/84045)              2/10/95...
**CB8291   ELEAT                    [no datasheet]                 c90...
**CB8295   ELEATsx                  [no datasheet]                 c90...
**82C100   IBM PS/2 Model 30/Super XT                                ?...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91
***Info:...
***Configurations:...
***Features:...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
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*Contaq  . . . . . [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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