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**82C100   IBM PS/2 Model 30/Super XT                                ?
***Info:
The 82C100 is a single chip implementation of most of the system logic
necessary to implement a super XT compatible system with PS/2 Model 30
functionality using either an  8086 or 8088 microprocessor. The 82C100
can  be used  with either  8 or  16-bit microprocessors.   The 82C100
includes features  which will enable  the PC manufacturer to  design a
super PS/2 Model 30/XT  compatible system with the highest performance
at  10  MHz  zero  wait   state  system  with  an  8086,  the  highest
functionality  With  dual  clock  and  2.5 MB  DRAM  (with  integrated
Extended Memory System control logic), the lowest power implementation
by  utilizing the on-chip  power management  features and  the highest
inte- gration with the lowest component count SMT design.

The 82C100 can be combined with CHIPs‘ 820601 Multifunction Controller
and 82C451 VGA Graphics Controller to provide a high performance, high
integration PS/2 Model 30 type system.

The 82C100 supports most of the peripheral functions on the P8/2 Model
30 planar board: 8284 compatible  clock generator with the option of 2
independent oscillators.   8288 compatible bus  controller, 8237 comp-
atible  DMA  controller, 8259  compatible  interrupt controller,  8254
compatible timer/counter, 8255 compatible peripheral I/O port, XT Key-
board interface,  Parity Generation and  Checking for DRAM  memory and
memory controller for DRAM and SRAM memory sub-systems.

The  82C100   enables  the  user   to  add  P8/2  Model   30  superset
functionality  on  the  planar  board: dual  clock  with  synchronized
switching between the two clocks, built-in Lotus-Intel-Microsoft (LIM)
EMS  support for  up to  2.5 Megabytes  of DRAM  and  power management
features  for SLEEP  mode as  well as  SUSPEND/RESUME  Operations. The
SLEEP and SUSPEND/RESUME features  help in preserving the battery life
in laptop portable applications.

The 82C100  Supports a very flexible memory  architecture. For systems
with DRAMs, the DRAM controller supports 64K, 256K and 1M DRAMs. These
DRAMs can be organized  in four banks of up to a  maximum of 2.5 MB on
the planar board.   The 2.5 MB memory can be  implemented with 2 banks
of  1M x  1 DRAMs,  partitioned locally  as 640KB  of real  memory and
1.875MB of EMS  memory, For systems which require  low operating power
and minimum  standby power dissipation,  the chips provide  the decode
logic which in conjunction  with external decoders allows selection of
up to  640KB of static RAM.  This option is useful  in laptop portable
applications.

The 82C100 is packaged in a 100-pin plastic flatpack.

***Configurations:...
***Features:...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
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*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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**SL82C490   'Wagner' 486?              [no datasheet]               ?
***Notes:...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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