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**CS8285 PEAKsx (82C836/82C835) c91
***Info:...
***Configurations:...
***Features:...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
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*Contaq . . . . . [no datasheets, some info]...
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**82396SX Smart Cache 12/17/90
***Notes:...
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**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**SL82C365 Cache Controller (for 386DX/SX) c:91
***Info:
The SL82C365 supports direct-mapped cache system with data size ranged
from 16KB to 1MB and line size ranged from 1 to 4 doublewords.
Without any external logic, SL82C365 supports 1 to 4 banks of cache
SRAMs independent of the line size. An 8-bit tag comparator is
integrated into the chip which not only saves on the system cost but
also improves the overall performance. 25ns tag SRAM and 35ns data
SRAM are adequate for zero wait state non-pipelined 33Mhz
operation. Assuming 8Kx8, 16Kx4, 32Kx8 and 64Kx4 SRAMs are used for
tag SRAM, the selectable organization is indicated in Table 1-1. [see
datasheet] More options are available for data RAM configurations
because of the flexibility in selecting the number of banks. Refer to
section 1.13 [see datasheet] for detailed design examples.
***Versions:...
***Features:...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
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