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*Chips & Technologies...
**CS8232   CMOS 386/AT              (82C301/302/303/304/305/306)   c86
***Notes:...
**CS8233   PEAK/386 AT (Cached)     (82C311/82C315/82C316)     c:Dec90...
**CS8236   386/AT                   (82C301/2/3/4/5/6/206)         c86...
**CS8237   TURBO CACHE-BASED 386/AT (82C301/7/3/4/5/6/206)         c86...
**CS8238   CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226)   c:Aug89...
**CS82310  PEAK/DM 386 AT           (82C351/82C355/82C356)         c91...
**CS8281   NEATsx (386SX)           (82C811/812/215/206)       c:Dec89...
**CS8283   LeAPset-sx               (82C841/82C242/82C636)     c:Mar90...
**CS8285   PEAKsx                   (82C836/82C835)                c91...
**CS8288   CHIPSlite-sx             (82C836/82C641/82C835)          c?...
**CS4000   WinCHIPS                 (64200/84021/84025)            c92...
**CS4021   ISA/486                  (84021/84025)                  c92...
**CS4031   CHIPSet                  (84031/84035)              5/10/93...
**CS4041/5 CHIPSet                  (84041/84045)              2/10/95...
**CB8291   ELEAT                    [no datasheet]                 c90...
**CB8295   ELEATsx                  [no datasheet]                 c90...
**82C100   IBM PS/2 Model 30/Super XT                                ?...
**82C110   IBM PS/2 Model 30/Super XT                                ?...
**82C235   Single Chip AT (SCAT)                                   c89...
**82C836   Single Chip 386sx (SCATsx)                              <91...
**F8680/A  PC/CHIP Single-Chip PC                                  c93...
**
**Support Chips:
**64200    (Wingine) High Performance 'Windows Engine'         c:Oct91...
**82C206   Integrated Peripheral Controller                        c86...
**82C601/A Single Chip Peripheral Controller                 <08/30/90...
**82C607   Multifunction Controller                             <Jun88...
**82C710   Universal Peripheral Controller                     c:Aug90...
**82C711   Universal Peripheral Controller II                  c:Jan91...
**82C712   Universal Peripheral Controller II                  c:Jan91...
**82C721   Universal Peripheral Controller III                 c:May93...
**82C735   I/O Peripheral Controller With Printgine            c:Jul93...
**82C835   Single CHIP 386sx AT Cache Controller               c:Apr91...
**F87000   Multi-Mode Peripheral Chip                         11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT25          3-volt Core Logic for 386SX                    c:Dec92
***Info:
The HT25  is the industry’s first  3-Volt single chip  core logic with
integrated  power management  for  386SX based  3-Volt systems.   Pro-
grammable  power  management features  give  system manufacturers  the
flexibility of offering customized system solutions.

GENERAL DESCRIPTION
The HT25 is a  PC/AT1M compatible single-chip solution with integrated
power management  designed to operate in a  3-Volt system environment.
This highly integrated chip facilitates  the design of low power, high
performance portable systems.  The  HT25 supports 3-Volt 386SX CPUs at
clock  speeds  up  to  25MHz  at  2.7V to  3.6V.   It  supports  power
management functions using the System Management Mode (SMM).

Flexible  power  management is  the  cornerstone  of the  HT25.   This
approach provides  power saving  features that  can be  customized for
product  differentiation.  Power  management  features include  system
activity monitors  and general purpose  I/O pins.  The  HT25 generates
System Management  Interrupt (SMI) to process  activity information or
when access  to powered down  peripherals is detected.   Further power
savings are achieved through the HT25’s ability to control CPU and NPU
clocks and support for slow refresh and self refresh DRAMs.

The HT25 Memory Controller features BIOS Shadowing, Memory Relocation,
EMS, Page  Mode Memory Access and Interleaving.  The memory controller
allows memory banks to be reordered to allow more efficient memory in-
terleaving. The HT25 supports 512Kb, le, and 4Mb DRAMs.

The HT25 architecture  is optimized for 3-Volt system  designs, the SD
bus acknowledge input provides a flexible I/O bus architecture and the
XD bus is buffered directly  from the HT25.  Further, no external data
bus buffers are required for a closed 3V system.

***Configurations:...
***Features:...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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