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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
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**82c801         SCWB2 DX Single Chip Solution                    c:92
***Notes:...
***Info:
The  82C801  SCWB2  can  be  summarized in  four  words:  integration,
performance,  features  and  reliability.   The  best  value  for  the
OEM/system house.

The SCWB2 is  the result of an engineering team driven  by the need to
provide  the fastest, most  reliable solutions  in the  smallest, most
cost effective package and having complete confidence in compatibility
and reliability of the product. With a feature set that doesn't take a
back seat to any solution in the market.

From the 50  MHz Write back Cache to complete  local bus support, this
chip is  everything a  system designer needs  to provide  his customer
with state-of-the-art solutions for high performance PCs in the market
today - and for some time to come.

The  SCWB2 is designed  for the  OEM/system house  who needs  a single
chip, local  bus, lightning performance, design  flexibility, 8 banks,
quick-to-market, and cost effectiveness.


***Configurations:...
***Features:...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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**W860551/P UART with FIFO and Printer Port Controller             <94
***Info:...
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***Features:...
**
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