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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
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Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
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**W860551/P UART with FIFO and Printer Port Controller <94
***Info:...
***Versions:...
***Features:
o Easily interfaces with most popular microprocessors
o Pin compatible and functionally compatible with the existing
W860451
o Centronics parallel interface
o Capable of running all existing 16450 and 16550 software
o Uses system's 14.3181 BMHz clock input
o In FIFO mode transmitter and receiver are each buffered with
16-byte FIFOs to reduce number of intercepts presented to the CPU
o Adds or deletes standard asynchronous communication bits (start,
stop, and parity) to or from serial data
o Independently controlled transmit, receive, line status, and data
set interrupts
o Programmable baud rate generator
o Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
o Fully programmable serial-interface characteristics:
- 5, 6, 7, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1, 1.5, or 2-stop bit generation
- Baud generation
o False start bit detection
o Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation
- Break, parity, overrun, framing error simulation
o Fully prioritized interrupt system controls
o 40-pin PDIP package for W860551 and 44-pin PLCC package for
W86C551P
**
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