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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
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*Unresearched:...
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*Western Digital...
*Winbond...
**W83628F/29D PCI TO ISA Bridge Set                                c98
***Info:...
***Configurations:...
***Features:...
**W83626F/D   LPC TO ISA Bridge Set                                <00...
**
**Multi I/O:
**W83757          SUPER I/O  CHIP                                  <92...
**W83767F         ??           Multi I/O  [no datasheet]
**W83777F/87F     Power I/O   (Multi I/O)                          <95...
**W83877F         WINBOND I/O (Multi I/O)                          <96...
**W83877TF/TG/TD  WINBOND I/O (Multi I/O)                          c97...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O)                          c97...
**W83977TF        WINBOND I/O (Multi I/O)                          c97...
**W83977EF        WINBOND I/O (Multi I/O)                          <98...
**W83977ATF       WINBOND I/O (Multi I/O)                          <98...
**
**Disk Controller:
**W83759/A/F/AF   Advanced VL-IDE Disk Controller                  <96...
**W83769          Local Bus IDE Solution                           <94...
**
**UARTS:
**W86C250A  UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter         <Jul89
***Info:...
***Versions:...
***Features:
o   Easily interfaces to most popular microprocessors.
o   Adds or deletes standard asynchronous communication bit (start, 
    stop, and parity) to or from serial data stream.
o   Holding and shift registers eliminate the need for precise 
    synchronization between the CPU and the serial data.
o   Independently controlled transmit, receive, line status, and data 
    set interrupts.
o   Programmable baud generator allow division of any input clock by 1 
    to (2^16 - 1) and generates the internal 16x clock.
o   Independent receiver clock input.
o   MODEM control functions (CTS, RTS. DSR, DTR, RI, and DCD).
o   Fully programmable serial-interface characteristics:
    - 5, 6, 7, or 8-bit characters
    - Even, odd, or no-parity bit generation and detection
    - l, 1.5 or 2-stop bit generation.
    - Baud generation (DC to 56K baud). 
o   False start bit detection.
o   Complete status reporting capabilities.
o   TRl-STATE TTL drive capabilities for bidirectional data bus and 
    control bus.
o   Line break generation and detection.
o   Internal diagnostic capabilities:
    - Loopback controls for communications link fault isolation.
    - Break, parity, overrun, framing error simulation.
o   Fully prioritized interrupt system controls.


**W86C451   I/O controller for IBM PC/AT/XT                     <Jul89...
**W86C452   I/O controller for IBM PC/AT                         Jul89...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...