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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**IBM AT: MC146818 Real Time Clock <84
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**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89
***Info:...
***Versions:...
***Features:
o Easily interfaces to most popular microprocessors.
o Adds or deletes standard asynchronous communication bit (start,
stop, and parity) to or from serial data stream.
o Holding and shift registers eliminate the need for precise
synchronization between the CPU and the serial data.
o Independently controlled transmit, receive, line status, and data
set interrupts.
o Programmable baud generator allow division of any input clock by 1
to (2^16 - 1) and generates the internal 16x clock.
o Independent receiver clock input.
o MODEM control functions (CTS, RTS. DSR, DTR, RI, and DCD).
o Fully programmable serial-interface characteristics:
- 5, 6, 7, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- l, 1.5 or 2-stop bit generation.
- Baud generation (DC to 56K baud).
o False start bit detection.
o Complete status reporting capabilities.
o TRl-STATE TTL drive capabilities for bidirectional data bus and
control bus.
o Line break generation and detection.
o Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation.
- Break, parity, overrun, framing error simulation.
o Fully prioritized interrupt system controls.
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
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