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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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*Unresearched:...
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*Winbond...
**W83877TF/TG/TD WINBOND I/O (Multi I/O) c97
***Info:
GENERAL DESCRIPTION
W83877TF/TG is an enhanced version from Winbond's most popular I/O
chip W83877F --- which integrates the disk drive adapter, serial port
(UART), IrDA 1.0 SIR, parallel port, configurable Plug-and-Play
registers for the whole chip --- plus additional powerful features:
ACPI / legacy power management, serial IRQ, and IRQ sharing.
The disk drive adapter functions of W83877TF/TG include a floppy disk
controller compatible with the industry standard 82077/765, data
separator, write pre-compensation circuit, decode logic, data rate
selection, clock generator, drive interface control logic, interrupt
and DMA logic. The wide range of functions integrated into W83877TF/TG
greatly reduces the number of components required for interfacing with
floppy disk drives. W83877TF/TG supports four 360K, 720K, 1.2M, 1.44M,
or 2.88M disk drives and data transfer rates of 250 Kb/S, 300 Kb/S,
500 Kb/S,1 Mb/S, and 2 Mb/S.
W83877TF/TG provides two high-speed serial communication ports
(UARTs), one of which supports serial Infrared communication. Each
UART includes a 16-byte send/receive FIFO, a programmable baud rate
generator, complete modem control capability, and a processor
interrupt system. One of the UARTs support infrared (IR) IrDA1.0. Both
UARTs provide legacy speed with baud rate up to 115.2K and provide
advanced speed with baud rate up to 230k, 460k, and 921k bps which
support higher speed Modems.
W83877TF/TG supports one PC-compatible printer port (SPP),
Bi-directional printer port (BPP) and also Enhanced Parallel Port
(EPP) and Extended Capabilities Port (ECP). Through the printer port
interface pins, also available are: Extension FDD Mode and Extension
2FDD Mode allowing one or two external floppy disk drives to be
connected. This function is especially valuable for notebook computer
applications.
Winbond W83877TF/TG provides functions that comply with ACPI (Advanced
Configuration and Power Interface), which includes support of legacy
and ACPI power management through SMI or SCI function pins. One
24-bits power management timer is implemented with the carry notify
interrupt. W83877TF/TG also has auto power management mode to reduce
the power consumption.
The serial IRQ for PCI architecture is supported, ISA IRQs
(IRQ1~IRQ15) can be cascaded into one IRQSER pin. W83877TF/TG also
features ISA bus IRQ sharing and allows two or more devices to share
the same IRQ pin.
W83877TF/TG is made to fully comply with Microsoft PC97 Hardware
Design Guide. IRQs, DMAs, and I/O space resources are flexible to
adjust to meet ISA PnP requirement. Moreover W83877TF/TG is made to
meet the specification of PC97's requirement in the power management:
ACPI and DPM (Device Power Management).
The configuration registers support mode selection, function
enable/disable, and power down function selection. Furthermore, the
configurable PnP registers are compatible with the Plug-and-Play
feature demand of Windows 95 , which makes system resource allocation
more efficient than ever.
Another benefit of W83877TF/TG is that it is pin-to-pin compatible to
W83877F, and all of the 100-pin Winbond I/O IC family. Thus makes the
design of applications very convenient and flexible.
***Versions:...
***Features:...
**W83977F/G/AF/AG WINBOND I/O (Multi I/O) c97...
**W83977TF WINBOND I/O (Multi I/O) c97...
**W83977EF WINBOND I/O (Multi I/O) <98...
**W83977ATF WINBOND I/O (Multi I/O) <98...
**
**Disk Controller:
**W83759/A/F/AF Advanced VL-IDE Disk Controller <96...
**W83769 Local Bus IDE Solution <94...
**
**UARTS:
**W86C250A UART (equivalent of INS8C250A) [no datasheet]
**W86C450/P Universal Asynchronous Receiver/Transmitter <Jul89...
**W86C451 I/O controller for IBM PC/AT/XT <Jul89...
**W86C452 I/O controller for IBM PC/AT Jul89...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
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