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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
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*SIS...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98
***Info:...
***Configurations:...
***Features:...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
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*Unresearched:...
*VIA...
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*Western Digital...
**WD7615     Desktop Buffer Manager                          <04/15/92
***Info:...
***Versions:...
***Features:
o   Allows the WD7XC10 based designs to work with a generic "Super l/O" 
    device or with the WD76C20 and WD76C30
o   Replaces majority of external "glue" logic, up to 13 devices:
    - AT bus address buffers with 24 mA drive
    - AT bus interrupt multiplexing, and interrupt pull ups.
    - AT bus DRQ multiplexing and internal pull downs.
    - Keyboard/mouse interrupt latching and clearing functions
    - A20 Gate logic
    - Controlling the IDE data bit 7 at address 3F7H.
o   Allows implementation of a desktop system with only three external 
    devices
o   Direct connect to AT address bus SA1 through SA19 and LA17 through 
    LA23 with 24 mA drive
o   DAC multiplexing and RESET generation
o   DRAM WE signal from WD76C10 inversion and buffering
o   SMEMR and SMEMW generation with 24mA direct drive
o   Divide by 2 or divide by 4 clock output
o   136-pin MQFP package



**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
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