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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
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*TI (Texas Instruments)...
**TACT82000   3-Chip 286 [no datasheet]                            c89
***Notes:...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE3400/B      80286-Based AT Compatible CPU Core Logic (12 MHz) c:86
***Info:...
***Configurations:...
***Features:...
**FE3500/B      80286-Based AT Compatible CPU Core Logic (12 MHz) c:87...
**FE3600/A/B/C  16/20MHz AT Chip set                              c:88...
**FE5300        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE5400        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE6500        CPU Core Logic for PS/2 Model 70/80 Compatibles   c:88...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91
***Notes:...
***Info:...
***Versions:...
***Features:
o   Two fully programmable and independent serial I/O ports 
    configurable as PC/AT compatible (WD16C452) or PS/2 
    compatible (WD16C552)
    - Loopback controls for communications link fault isolation for 
      each ACE
    - Line break generation and detection for each ACE
    - Complete status reporting capabilities
    - Generation and stripping of serial asynchronous data control 
      bits (start, stop, parity)
    - Programmable baud rate generator and MODEM control signals for 
      each port
    - Programmable baud rate generator input clock
    - Optional 16 byte FIFO buffers on both transmit and receive of 
      each port for CPU relief during high speed data transfer
    - Programmable FIFO threshold levels of 1 , 4, 8, or 14 bytes on 
      each port
o   Parallel port configurable as a fully Centronics or PS/2 
    compatible, bidirectional parallel port
o   Independently programmable parallel port
o   Interrupt multiplexing logic
    - Selectable multiplexing logic for connecting PC/AT interrupt 
      request lines to the WD76C10 single chip AT controller
o   Clock generation circuitry
    - 80287 coprocessor clock generation
    - WD76C10 and floppy controller clock generation
    - 8042 keyboard clock generation
o   Built-in testability features
o   Hardware or software controllable sleep mode
o   CMOS implementation for high speed and low power requirements 
o   Pulse extension on IRQ inputs
o   84-pin PLCC and PQFP packages

**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
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