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**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97
***Info:...
***Configuration:...
***Features:
o Support Intel Pentium CPU and other compatible CPU host bus at
50/55/60/66/75 MHz
o Support CPU with MMX feature
o Support the Pipelined Address Mode of Pentium CPU
o Support the Full 64-bit Pentium Processor data Bus
o Meet PC97 Requirements
o Integrated Second Level (L2) Cache Controller
- Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Cache Organization
- Integrated 16K bits Dirty RAM
- Support Pipelined Burst SRAM
- Support 256 KBytes and 512 KBytes Cache Sizes
- Cache Hit Read/Write Cycle of 3-1-1-1
- Cache Back-to-Back Read/Write Cycle of 3-1-1-1-1-1-1-1
o Integrated DRAM Controller
- Support 6 RAS Line (3 Banks) of FPM/EDO/SDRAM DIMMs/SIMMs
- Support 2Mbytes to 384Mbytes of main memory
- Support Cacheable DRAM Sizes up to 128 MBytes.
- Support 256K/512K/1M/2M/4M/8M/16M/32M x N FPM/EDO/SDRAM DRAM
- Support 64 Mb DRAM Technology
- Support 3.3V or 5V DRAM.
- Supports Symmetrical and Asymmetrical DRAM.
- Support 32 bits/64 bits mixed mode configuration
- Support Concurrent Write Back
- Support CAS before RAS Refresh
- Support Relocation of System Management Memory
- Programmable CAS#, RAS#, RAMWE# and MA Driving Current.
- Fully Configurable for the Characteristic of Shadow RAM (640
KBytes to 1 MBytes)
- Support FPM DRAM 5-3-3-3(-3-3-3-3) Burst Read Cycles
- Support EDO DRAM 5-2-2-2(-2-2-2-2) Burst Read Cycles
- Support SDRAM 6-1-1-1(-2-1-1-1) Burst Read Cycles
- Support X-1-1-1/X-2-2-2/X-3-3-3 Burst Write Cycles
- Support 8 Qword Deep Buffer for Read/Write Reordering, Dword
Merging and 3/2-1-1-1 Post write Cycles
- Two Programmable Non-Cacheable Regions
- Option to Disable Local Memory in Non-Cacheable Regions
- Shadow RAM in Increments of 16 KBytes
o Integrated PMU Controller
- Meet ACPI Requirements
- Support Both ACPI and Legacy PMU
- Support Suspend to Disk
- Support SMM Mode of CPU
- Support CPU Stop Clock
- Support Power Button for ACPI function
- Support Automatic Power Control for system power off function
- Support Modem Ring-in, RTC Alarm Wake up
- Support Thermal Detection
- Support GPIOs, and GPOs for External Devices Control
- Support Programmable Chip Select
o Provides High Performance PCI Arbiter.
- Support up to 5 PCI Masters
- Support Rotating Priority Mechanism
- Hidden Arbitration Scheme Minimizes Arbitration Overhead.
- Support Concurrency between CPU to Memory and PCI to PCI
o Integrated Host-to-PCI Bridge
- Support Asynchronous and Synchronous PCI Clock
- Translates the CPU Cycles into the PCI Bus Cycles
- Provides CPU-to-PCI Read Assembly and Write Disassembly
Mechanism
- Translates Sequential CPU-to-PCI Memory Write Cycles into PCI
Burst Cycles
- Zero Wait State Burst Cycles
- Support IDE Posted Write
- Support Pipelined Process in CPU-to-PCI Access
- Support Advance Snooping for PCI Master Bursting
- Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes
o Integrated Posted Write Buffers and Read Prefetch Buffers to
Increase System Performance
- CPU-to-Memory Posted Write Buffer (CTMFF) with 8 QW Deep,
Always Sustains 0 Wait Performance on CPU-to-Memory.
- CPU-to-Memory Read Buffer with 4 QW Deep
- CPU-to-PCI Posted Write Buffer(CTPFF) with 8 DW Deep
- PCI-to-Memory Posted Write Buffer(PTHFF) with 8 QW Deep,
Always Streams 0 Wait Performance on PCI-to/from-Memory Access
- PCI-to-Memory Read Prefetch Buffer(CTPFF) with 8 QW Deep
o Integrated PCI-to-ISA Bridge
- Translates PCI Bus Cycles into ISA Bus Cycles
- Translates ISA Master or DMA Cycles into PCI Bus Cycles
- Provides a Dword Post Buffer for PCI to ISA Memory cycles
- Two 32 bit Prefetch/Post Buffers Enhance the DMA and ISA Master
Performance
- Fully Compliant to PCI 2.1
o Enhanced DMA Functions
- 8-, 16- bit DMA Data Transfer
- ISA compatible, and Fast Type F DMA Cycles
- Two 8237A Compatible DMA Controllers with Seven Independent
Programmable Channels
- Provides the Readability of the two 8237 Associated Registers
- Support Distributed DMA
o Built-in Two 8259A Interrupt Controllers
- 14 Independently Programmable Channels for Level- or Edge-
triggered Interrupts
- Provides the Readability of the two 8259A Associated Registers
- Support Serial IRQ
o Three Programmable 16-bit Counters compatible with 8254
- System Timer Interrupt
- Generates Refresh Request
- Speaker Tone Output
- Provides the Readability of the 8254 Associated Registers
o Built-in Keyboard Controller
- Hardwired Logic Provides Instant Response
- Support PS/2 Mouse interface
- Support Hot Key "Wake-up" Function
- Capable of Enable/Disable Internal KBC and PS2 Mouse
o Built-in Real Time Clock(RTC) with 256B CMOS SRAM
- Built-in up to one Month Alarm for ACPI
o Fast PCI IDE Master/Slave Controller
- Bus Master Programming Interface for ATA Windows 95 Compliant
Controller
- Support PCI Bus Mastering
- Plug and Play Compatible
- Support Scatter and Gather
- Support Dual Mode Operation - Native Mode and Compatibility
Mode
- Support IDE PIO Timing Mode 0, 1, 2 ,3 and 4
- Support Multiword DMA Mode 0, 1, 2
- Support Ultra DMA/33
- Two Separate IDE Bus
- Two 16 Dword FIFO for PCI Burst Transfers.
o Universal Serial Bus Host Controller
- OpenHCI Host Controller with Root Hub
- Two USB ports
- Support Over Current Detection
- Support Legacy Devices
o Support I2C serial Bus
o Support the Reroutibility of the four PCI Interrupts
o Support 2Mb Flash ROM Interface
o Support NAND Tree for ball connectivity testing
o 553-Balls BGA Package
o 0.35μm 3.3V Technology
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91
***Info:...
***Versions:...
***Features:...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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