[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95
***Info:
The SiS 486-VIP (VESA/ISA/PCI) chips are two-chip solution ideally for
Intel's 80486, SL Enhanced 486, P24D/P24T/DX4 CPU, AMD's 486, Enhanced
Am486 and Cyrix's Cx486 (M7)/Cx 5x86 CPU based on green AT system. By
supporting the most popular industrial standard system interfaces, it
provides flexible configurations for system design and applications.
The SiS85C496 PCI & CPU Memory Controller (PCM) integrates the Host
Bridge (Host Interface), the cache and main memory DRAM Controller,
the PCI Bridge, the built-in IDE Controller, and the FS-Link Bus (Fast
Slow Link Bus). It provides the address paths and bus control for
transfers among the Host (CPU/L1 cache), main memory (L2 cache and
DRAM), the Peripheral Component Interconnect (PCI) Bus, and the
FS-Link Bus. The L2 cache controller supports both write-through and
write-back cache policies and cache sizes up to 1 MBytes. The cache
memory can be built using standard asynchronous SRAMs. The main
memory DRAM controller interfaces DRAM to the Host Bus, PCI Bus, and
FS-Link Bus. Up to eight single sided SIMMs or four double sided SIMMs
provide a maximum of 255 MBytes of main memory. The installation of
DRAM SIMMs is "Table-Free", which allows the SIMMs be installed into
any slot location and any combinations. The built-in IDE hard disk
controller allows CPU accessing hard disk and also provides higher
system integration with lower system cost. The 85C496 is intended to
be used with the SiS85C497 which is a AT Bus Controller with built-in
206 controller.
The SiS85C497 AT Bus Controller and Megacells (ATM) provides the
interface between PCI/CPU/Memory Bus (fast machine) and the ISA Bus
(slow machine). It also integrates many of the common I/O functions
in today's ISA based PC systems. The 85C497 comprises the FS-Link
interface (Fast-Slow Link interface), ISA bus controller , DMA
controller and data buffers to isolate the FS-Link Bus from the ISA
Bus and to enhance performance. It also integrates a 14 channel
edge/level interrupt controller, refresh controller, a 8-bit BIOS
timer, three programmable timer/counters, non-maskable-interrupt (NMI)
control logic, Power Management Unit, and RTC. Figure 1 .1 [see
datasheet] shows the system block diagram.
***Configurations:...
***Features:...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**WD8110 System controller for 80386DX/486 <11/30/93
***Notes:...
***Info:
1.0 INTRODUCTION
The WD8110/LV System Controllers are designed to provide a high
performance, single chip system controller supporting all 80486SX,
80486DX. 80386SX and 80386DX CPUs in AT bus based Desktop/
Laptop/Notebook/Pen-based systems.
1.1 DOCUMENT SCOPE
This document describes the function and operation of the WD8110/LV
System Controller devices. It includes the description of external
logic necessary for efficient use of these devices. The WD8110/LV is
also referred to in this document as the System Controller.
1.3 WD8110/LV POWER MANAGEMENT
Power Management Control (PMC) is used for powering down the processor
or peripherals and includes processor stop clock, slow clock, auto-
matic processor clock speed switching modes and CAS before RAS slow
refresh. Suspend and resume is supported and low power DRAM is
refreshed while the processor and other power consuming devices are
turned off. The power drain for the core logic and VGA controller is
less than 2 mA in this mode. Power and clock speed may be controlled
by the Keyboard Controller. transparently to the 80386 or 80486.
The System Activity Monitor (SAM) is a transparent feature that
replaces the functions previously performed by software. It senses
when the system has been idle for a previously programmed period at
time and determines a clean break point in which to perform power down
activities such as suspend.
The system controller also supports System Management Interrupt (SMI)
with complete I/O trapping of up to six separate I/O ranges. Each
range has an independent timer which can generate an SMI after a
programmed period of time during which there was no I/0 access to that
range.
1.3.1 Desktop Applications
The WD8110/LV provides a high performance solution with a flexible
memory controller architecture. including support for five banks of
memory. The WD8110/LV can fully support an external look-aside cache
or a combination primary and secondary cache. This feature makes it
particularly suitable for use with cached microprocessors where it
maintains cache coherency via its built-in bus snooping capability. In
addition. the WD8110/LV supports Video Local Bus Interface (VLBI) for
enhanced graphics performance.
The built-in power management features of the WD8110/LV allows a high
performance yet power efficient desk top solution.
1.3.2 Portable Applications
The WD8110LV is an ideal choice because of its advanced power
management features and power saving 3.3 volt operation, which
delivers long battery life in a compact footprint. This makes it a
perfect choice for laptop, notebook, pen-based and palmtop computers.
The five bank memory controller on the WD8110LV provides the user with
great flexibility in the selection of 3.3 volt DRAMs to meet system
memory requirements in low voltage platforms. The WD8110LV memory
controller supports JEDEC standard 3.3 volt DRAM in various
configurations, including the JEIDA standard 88-pin DRAM card.
The WD8ll0/LV can be paired with the appropriate support devices from
Western Digital to deliver the most efficient solution for any
platform. For 5 volt desktop or portable platforms, the WD8l10/LV can
be used with the WD76C20 Peripheral Controller and the WD76C30 I/O
Controller. The WD8110 may also be used with the WD7615 Buffer Manager
device and a generic Super I/O chip to implement a low cost desktop
platform. For 3.3 volt applications, the WD8110LV can be used with the
WD76C20ALV and WD76C30ALV, both of which incorporate level translators
(split rail operation). For subnotebook and palmtop type applications,
WD7625LV buffer manager and WD8120LV Super I/O can be added to the
WD8110LV based solution to achieve a very compact footprint.
The WD8110/LV is a fifth generation system controller device derived
from core chips with proven compatibility and design maturity in
several of the industry's leading desktop and portable platforms.
Designed with the state of the art 0.9 micron high performance CMOS
process. the WD8110/LV family maintains architectural compatibility
with Western Digital's WD7600 and WD7855 systems logic chip sets while
incorporating many additional performance enhancements.
***Configurations:...
***Features:...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
(c) Copyright mR_Slugs Warehouse - All rights Reserved