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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Logicstar...
**SL9025  Address Controller                                    <oct88
***Info:...
***Versions:...
***Features:...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
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**FE3600/A/B/C  16/20MHz AT Chip set                              c:88
***Notes:...
***Info:
****General:...
****FE3001  AT CONTROL LOGIC...
****FE3010B AT PERIPHERAL CONTROL LOGIC...
****FE3021  ADDRESS BUFFER AND MEMORY CONTROLLER
The  FE3021  device  is   designed  to  reduce  chip  count,  increase
flexibility,  and provide improved  operating speed  and functionality
when used with  the FE3001, FE301O, and FE3031  devices to implement a
low cost, high performance AT compatible computer.

Chip count  is reduced  by integrating the  memory controller,  AT bus
address buffers, and I/O , Manager functions into one chip.

The memory controller is  a high performance design, with programmable
modes  of operation.  It controls  page mode  DR.A.M or  static column
DRAM.

Up to 4  banks of DRAM may be controlled. The  DRAM bank locations are
programmable  on 128K byte  boundaries. One  memory bank  allows split
addressing, so that  one portion may be placed  in conventional memory
with  the remainder  in extended  memory, with  an additional  mode to
allow copying BIOS code from ROM to RAM for faster execution.

A major function of the FE3021  is to generate chip select decodes for
peripheral  chips  on  the  system  board, for  instance,  the  floppy
controller, hard disk controller, serial, and parallel port chips. The
floppy and  hard disk chip selects  may be disabled or  may be enabled
for  either the  primary or  secondary address  decode, as  defined by
IBM.  Four programmable  chip  selects are  available, for  supporting
serial, parallel, mouse, or other types of ports.

****FE3031  AT DATA BUFFER...
***Configurations:...
***Features:...
**FE5300        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE5400        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE6500        CPU Core Logic for PS/2 Model 70/80 Compatibles   c:88...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...