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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89
***Notes:...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87
***Notes: ...
***Info:
****General:...
****FE3000A CPU control logic...
****FE3010/B Peripheral control logic...
****FE3020 Address buffer...
****FE3030 Data buffer...
****FE3040 I/O manager device
The FE3040 device is designed to reduce chip count, increase
flexibility, and provide improved operating speed and functionality
when used with other Western Digital peripheral chips on a PC~AT
compatible system board.
Chip count is reduced by integrating appropriate random logic and
logic formerly implemented with PALS. Flexibility is retained by
making the PAL type logic software programmable, so that
characteristics may be changed by different versions of BIOS ROMS or
through a BIOS ROM set-up program. Programmability also greatly
reduces the number of jumpers on the system board.
A major function of the FE3040 is to generate chip select decodes for
peripheral chips on the system board, for instance, the floppy
controller, hard disk controller, serial, and parallel port
chips. System operating speed may be optimized by tailoring the number
of processor wait states to each individual peripheral device. An
early generation of the IOCSl6 signal is also provided, since this
signal is in a critical timing path in high speed AT compatibles.
To reduce chip count and improve performance, particularly when an EGA
graphics controller is placed on the system board, separate blocks of
ROM may be mapped into a single physical ROM. For instance, the EGA
BIOS and standard BIOS may be placed into the same pair of ROM chips
or into a single 16 bit wide ROM. Besides reducing chip count, EGA
operating speed will be improved, since EGA BIOS will be accessed 16
bits at a time. To improve BIOS performance, ROM code may be copied
into excess RAM, and the BIOS ROM mapped out and replaced by RAM 16K
bytes at a time. (Excess RAM is the 384K left over after the lower
640K out of a 1 MB RAM is used).
Clock switching circuitry is included, which provides glitch free
switching between two unrelated clocks under BIOS control. In
addition, the processor clock output frequency may be programmed to be
divided by two. The clocks will typically be at a frequency of 12 MHz
to 24 MHz. In addition, the clock may be programmed to automatically
divide by 2 when expansion cards are accessed, to provide
compatibility with slow expansion cards while allowing full speed
execution when accessing system board RAM, ROM, and I/O.
***Configurations:...
***Features:...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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