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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*HMC (Hulon Microelectronics)...
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*Motorola...
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**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89
***Notes:...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
**FE3500/B 80286-Based AT Compatible CPU Core Logic (12 MHz) c:87
***Notes: ...
***Info:
****General:
The FE3500 chip set provides all necessary core logic, memory and I/O
control to build a complete integrated IBM compatible motherboard
using the 16-bit Intel 80286 Central Processing Unit.
It permits a fully functional 80286 AT to be consolidated into a very
small form factor and provides the means to embed communications,
storage and video control functions directly on the motherboard. It is
100% AT hardware and software compatible.
The FE3500 chip set consists of five devices: FE3000A, FE3010, FE3020,
FE3030 and FE3040. They operate at software selectable CPU clock rates
of 6, 8, 10 and 12.5 MHz.
The FE3500 chip set has 4 programmable I/O decodes that accommodate
additional peripheral adapters via an expansion bus. Running at up to
8 MHz, its Direct Memory Access (DMA) logic requires one wait state.
The high level of cohesion and compatibility between devices, all in
low-power CMOS, significantly facilitates design and implementation of
AT compatible system boards that are smaller, less noisy and consume
less power.
Components
The FE3000A AT CPU Control Logic integrates all control logic
supporting the 80286 microprocessor. It contains both processor and
coprocessor support logic, wait state generator logic, 256K and 1MB
RAM support logic, and operates at 6, 8, 10 and 12.5 MHz clock speeds.
The FE3010 AT Peripheral Control Logic contains 15 interrupt channels,
3 timer channels, 7 DMA channels and supports both 256K and 1 MB RAM
chips. It supports the 8 MHz DMA operations.
The FE3020 AT Address Buffer Integrated Circuit incorporates address
buffers and memory read/write control buffers. The FE3030 Data Buffer
Integrated Circuit incorporates the AT system data buffers and control
logic.
The FE3040 I/O Manager integrates much of the logic formerly
implemented with PALS. It consolidates enhanced multi-speed control
logic and decode/mapping logic. It has the ability, through software,
to synchronously change system clock speeds. In addition to reducing
component count, the I/O Manager increases functional flexibility and
performance by optimizing both system and peripheral clock speeds.
The I/O Manager also provides a Hot Reset feature which permits
software conversion from protected mode to real mode without a hard
reset.
Clock Speed Management
The FE3040 I/O Manager chip generates chip select decodes for system
board resident peripheral chips like the floppy controller, hard disk.
controller, serial port chip or parallel port chip.
It decouples the peripheral bus to support programmable bus speeds and
wait states. This enables full speed CPU local operations with only
selected bus accesses running at slower compatibility speeds. Early
generation of the IOCSl6 signal provides for the critical 16-bit I/O
peripheral timing path in high-speed AT compatibles. Overall system
performance is greatly enhanced.
Enhanced BIOS Management
Both EGA BIOS and system BIOS can be placed into the same pair of ROM
chips or share a single 16-bit wide ROM. The I/O Manager can map the
BIOS from slower ROM to faster read-only designated RAM on
power-up. It can also split the 8-bit EGA BIOS into 16-bits for faster
execution.
Memory Management
The FE3500 chip set supports the DOS defined 640K of memory in 64K
block increments on the local bus. Either 256K or 64K RAMs can be used
depending on system cost and configuration objectives. The BIOS EPROM
resides on the local bus in the top 64K of memory.
A Cost Effective Design
The FE3500 chip set is cost effective because it reduces overall
component count, board space and power requirements.
Fully functional AT motherboard circuitry can be consolidated into a
very small form factor (less than 35 square inches) leaving sufficient
room in most designs to embed additional functions such as
standardized floppy, hard disk, video, communications and imaging
control. The FB3500 chip set provides exceptional flexibility.
All programmable, characteristics may be changed by different versions
of BIOS ROMS or through a BIOS ROM set-up program. This
programmability greatly reduces the number of required configuration
jumpers on the system board. A system configuration register
eliminates external dip-switches.
Packaging
The FE3000A, FE3010, FE3020 and FE3030 are packaged in 84-pin,
J-leaded surface-mountable plastic chip carriers. The FE3040 is
packaged in a 68-pin, J-leaded surface-mountable plastic chip carrier.
****FE3000A CPU control logic...
****FE3010/B Peripheral control logic...
****FE3020 Address buffer...
****FE3030 Data buffer...
****FE3040 I/O manager device...
***Configurations:...
***Features:...
**FE3600/A/B/C 16/20MHz AT Chip set c:88...
**FE5300 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE5400 CPU Core Logic for PS/2 Model 50/60 Compatibles c:87...
**FE6500 CPU Core Logic for PS/2 Model 70/80 Compatibles c:88...
**WD6400SX/LP CPU Core Logic for PS/2 386SX Compatibles <90...
**WD6500 CPU Core Logic for PS/2 386DX/486 Compatible <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX <11/25/91...
**WD7700/LP System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855 System controller for 80386SX <09/25/92...
**WD7900/LP/LV System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110 System controller for 80386DX/486 <11/30/93...
**
**Support Chips:
**WD76C20x Floppy, RTC, IDE and Support Logic Device <11/25/91...
**WD76C30x Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615 Desktop Buffer Manager <04/15/92...
**WD7625 Desktop Buffer Manager <10/01/92...
**WD8120LV Super I/O [no datasheet] ?
**Other Chips:...
*Winbond...
*ZyMOS...
*General Sources:...
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