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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**?????  (Profusion)    c:99...
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**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88
***Info:...
***Versions:...
***Features:...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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*Western Digital...
**FE3500/B      80286-Based AT Compatible CPU Core Logic (12 MHz) c:87
***Notes:	...
***Info:
****General:...
****FE3000A  CPU control logic...
****FE3010/B Peripheral control logic...
****FE3020   Address buffer...
****FE3030   Data buffer...
****FE3040   I/O manager device
The  FE3040  device  is   designed  to  reduce  chip  count,  increase
flexibility,  and provide improved  operating speed  and functionality
when  used with  other Western  Digital  peripheral chips  on a  PC~AT
compatible system board.

Chip  count is  reduced by  integrating appropriate  random  logic and
logic  formerly  implemented with  PALS.  Flexibility  is retained  by
making   the   PAL  type   logic   software   programmable,  so   that
characteristics may be  changed by different versions of  BIOS ROMS or
through  a  BIOS  ROM  set-up program.  Programmability  also  greatly
reduces the number of jumpers on the system board.

A major function of the FE3040  is to generate chip select decodes for
peripheral  chips  on  the  system  board, for  instance,  the  floppy
controller,   hard  disk   controller,  serial,   and   parallel  port
chips. System operating speed may be optimized by tailoring the number
of  processor wait  states to  each individual  peripheral  device. An
early generation  of the  IOCSl6 signal is  also provided,  since this
signal is in a critical timing path in high speed AT compatibles.

To reduce chip count and improve performance, particularly when an EGA
graphics controller is placed on  the system board, separate blocks of
ROM may  be mapped into a  single physical ROM. For  instance, the EGA
BIOS and standard  BIOS may be placed into the same  pair of ROM chips
or into  a single 16 bit  wide ROM.  Besides reducing  chip count, EGA
operating speed will  be improved, since EGA BIOS  will be accessed 16
bits at  a time. To improve  BIOS performance, ROM code  may be copied
into excess RAM,  and the BIOS ROM mapped out and  replaced by RAM 16K
bytes at  a time. (Excess  RAM is the  384K left over after  the lower
640K out of a 1 MB RAM is used).

Clock  switching circuitry  is  included, which  provides glitch  free
switching  between  two  unrelated   clocks  under  BIOS  control.  In
addition, the processor clock output frequency may be programmed to be
divided by two. The clocks will  typically be at a frequency of 12 MHz
to 24 MHz.  In addition, the clock may  be programmed to automatically
divide   by  2  when   expansion  cards   are  accessed,   to  provide
compatibility  with slow  expansion  cards while  allowing full  speed
execution when accessing system board RAM, ROM, and I/O.

***Configurations:...
***Features:...
**FE3600/A/B/C  16/20MHz AT Chip set                              c:88...
**FE5300        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE5400        CPU Core Logic for PS/2 Model 50/60 Compatibles   c:87...
**FE6500        CPU Core Logic for PS/2 Model 70/80 Compatibles   c:88...
**WD6400SX/LP   CPU Core Logic for PS/2 386SX Compatibles          <90...
**WD6500        CPU Core Logic for PS/2 386DX/486 Compatible       <90...
**WD7600A/LP/LV System Chip Set for 80286 or 80386SX         <11/25/91...
**WD7700/LP     System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD7855        System controller for 80386SX                <09/25/92...
**WD7900/LP/LV  System Chip Set for 80286 or 80386SX (Cache) <11/25/91...
**WD8110        System controller for 80386DX/486            <11/30/93...
**
**Support Chips:
**WD76C20x   Floppy, RTC, IDE and Support Logic Device       <11/25/91...
**WD76C30x   Perip. Ctrl, Interrupt Multiplex, and Clock Gen <11/18/91...
**WD7615     Desktop Buffer Manager                          <04/15/92...
**WD7625     Desktop Buffer Manager                          <10/01/92...
**WD8120LV   Super I/O [no datasheet]                                ?
**Other Chips:...
*Winbond...
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