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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91
***Info:
The SL82C470 chip set provides  a very high performance.  highly inte-
grated and cost-effective implementation for personal computer systems
based on the  standard EISA bus.  It supports  both 386DX and 486DX/SX
CPUs over the entire performance range, from 20Mhz to 50Mhz.  The chip
set  can  operate in  either  "conventional"  or "concurrent"  config-
uration.  Under the conventional configuration, the cache subsystem is
dedicated to bus snooping when  a DMA or master device becomes active.
Under the concurrent  configuration, the CPU-cache operation continues
while  bus snooping  is  performed for  the  DMA or  master device  to
explore maximum  concurrency between the  CPU and the EISA  bus.  Only
ten  TTLs are  required for  a complete  motherboard design  under the
conventional  configuration in  addition to  the chip  set  and memory
devices.  Five  additional  TTLs   are  required  for  the  concurrent
configuration.  A complete EISA  system of either configuration can be
easily implemented on a baby AT sized motherboard.

The  SL82C470 chip  set consists  of three  160-pin PQFP  devices: the
SL82C471  integrated  cache/DRAM  controller,  the SL82C472  EISA  bus
controller and the SL82C473 DMA controller.

SL820471 Cache/DRAM Controller

The  SL82C47l  Cache/DRAM  controller  controls  the  cache  and  DRAM
accesses from  the CPU,  EISA/ISA masters and  DMA devices.   The chip
adapts a write-back cache  scheme to minimize the interference between
the CPU-cache and DMA/master  during their concurrent operations.  The
cache  size ranges from  64KB to  1MB with  advanced features  such as
2-1-1-1  burst  line fill.   Snoop-filtering,  local  bus support  and
programmable non-cacheable and  write-protected regions. The page mode
DRAM controller supports 1 to 4 banks of DRAMS up to 256MB.  A mixture
of 256KB, 1MB.  4MB and 16MB DRAMs is supported.  The video and system
BIOS  can  be  shadowed   or  cached  independently.   The  cache-DRAM
subsystem allows zero wait state burst mode DMA transfers to take full
advantage of the high bandwidth of the EISA bus.

The DRAM  data bus can either  be connected directly to  the CPU local
bus or  be buffered externally,  The control signals for  the external
buffers are generated by the SL82C471.

SL82C472 EISA Bus Controller

The  SL82C472  EISA  bus  controller translates  bus  control  signals
between the  CPU, EISA/ISA and DMA  masters and slaves.  The chip also
includes buffers  and byte/word swap  logic between the CPU  (or DRAM)
and the EISA bus. The  bus conversion and data alignment are performed
automatically.

The  SL82C472 includes two  8259 interrupt  controllers and  four 8254
timer channels  modified for 100%  EISA compatibility.  The  chip also
includes parity generation and check logic and NMI and timeout logic.

SL82C473 EISA DMA Controller

The SL82C473  DMA controller implements  seven EISA DMA  channels. the
system arbiter and the co-processor interface logic.  The DMA control-
ler  supports compatible  type  A,  type B  and  type  C (burst)  mode
operations  with  the  buffer  chaining  capability.   The  multilevel
rotating priority  arbitration with  fail-safe timeout  is implemented
for the  system arbiter.  Six  sets of slot-specific  master handshake
signals (MACK  and MREQ)  are provided  directly without  any external
components.

The address latches and buffers for  the EISA bus are also included in
the SL82C473.

***Configurations:...
***Features:...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
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**VL82C114 Combination I/O chip                                      ?
***Info:...
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**Not sure if they actually exist...
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