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**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
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**55x SoC (System-on-chip) <03/14/02
***Notes:...
***Versions:...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
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*Unresearched:...
*VIA...
*VLSI...
**VL82C481 System/Cache/ISA bus Controller c92
***Basics:...
***Info:
The VL82C481 controller is designed to control 486DX or
486SX/487SX-based ISA bus systems operating at up to 40 MHz. It also
supports 486 family CPUs that contain an integrated write-back cache
(P24T, etc.) The VL82C481 replaces the following devices on the
motherboard:
o Two 82C37A DMA controllers
o Two 82C59A interrupt controllers
o 82C54 timer
o 74LS612 memory mapper
o 82284 clock generator and ready interface
o 82288 bus controller
The following controller blocks are also included on-chip:
o Memory/refresh controller
o Port B and NMI logic
o Bus steering logic
o Turbo Mode control logic
o Parity checking logic
o Parity generation logic
o Writ-back look-aside cache controller
The VL82C481 supports the Weitek 4167 Numeric Coprocessor.
The memory controller logic is capable of accessing up to 64 MB. There
can be up to four banks of 256K, 1M, or 4M DRAMs used in a system. The
VL82C481 can drive two banks without external buffering. Built-in Page
Mode operation and up to two-way interleaving allows the PC designer
to maximize system perform- ance using low-cost DRAMs. Programmable
DRAM timing is provided for RAS# pre- charge, RAs-to-CAS delay, and
CAS# pulse width.
The VL82C481 write-back cache controller logic supports one or two
bank direct map write-back cache with external tag storage. The cache
controller can per- form 2-1-1-1 reads with two banks or 2-2-2-2 reads
with one bank. It can also perform 3-2-2-2 cycle reads for support of
slower SRAMs at higher frequences. The VL82C481 can perform one wait
state writes on cache-hits. An optional zero wait state write mode is
provided for use with fast cache SRAMs. The cachable DRAM range
includes 2 MB up to 64 MB utilizing cache data SRAM sizes of 32 KB
through 1 MB, respectively.
The HITM# input is provided to force the VL82C481 to abort DRAM or
cache cycles when a hit on a dirty line in the CPU write-back cache is
detected. the DRAM or cache cycle is subsequently restarted after the
CPU has written back the dirty data
Shadowing features are supported on 16K boundarys between A0000h and
FFFFFh (640 KB to 1 MB). simultaneous use of shadowed ROM and direct
system board access is possible in a non-overlapping fashion
throughout this memory space. Control over four access options is
provided:
1. Access ROM or slot bus for reads and writes.
2. Access system board DRAM for reads and writes.
3. Access system board DRAM for reads and slot bus for writes.
4. Shadow setup mode. Read ROM of slot bus, write system board DRAM.
Three special programmable address regions are provided. the Fast Bus
Clock Reg- ion allows accesses to certain memory regions at a faster
ISA bus clock rate for fast on-board or off-board devices. A
Non-Cacheable Region and/or a Write-Pro- tected Region may be defined
by a set of six registers that allow memory in the region 640 KB to 1
MB to be marked as non-cacheable and/or write-protected in increments
of 16 KB. A further set of registers allows a memory range anywhere in
the first 64 MB of memory to be marked as a DRAM region, an ISA bus
region, or a local bus region, either cachable or non-cacheable in
increments of 2 KB. 64 KB, or 1 MB.
Further support for devices that reside on the local bus is provided
through use of the LDEV# (Local Bus Access) input, which deselects the
VL82C481 during CPU cycles and causes the VL82C481 to generate VL-Bus
memory cycles when active dur- ing DMA and Master Mode cycles. Also, a
memory range anywhere in the first 64 MB of memory can be programmed
via the internal mapping registers. This allows the VL82C481 to access
a VL-Bus device during DMA or Master Mode transfers, and de- select
the VL82C481 during CPU cycles.
The VL82C481 handles system board refresh directly ans also controls
the timing of slot bus refresh. Refresh may be performed in three
different modes: synchro- nous, Asynchronous or Decoupled Mode. In the
Synchronous Mode, slot bus and on- board DRAM refresh cycles proceed
simultaneously with all memory cycles held until both have
completed. The Asynchronous Mode allows in- and off-board refre- shes
to be initiated simultaneously, but to complete asynchronously,
allowing earlier access to DRAM. In the Decoupled Mode, a separate
refresh counter is used for slot bus refresh, allowing on-board DRAM
and system refreshes to proceed in- dependently, with DRAM refreshes
initiated during bus idle cycles. CAS-before-RAS refresh is also
supported. Refreshes are staggered to minimize power supply loading
and attenuate noise on the VDD and VSS pins. The VL82C481 supports the
ISA bus standard refresh period of 15.625 us as well as 125 us.
The interrupt controller logic consists of two 82C59A megacells with
eight inter- rupt request lines each. The two megacells are cascaded
internally and three of the interrupt request inputs are connected to
internal circuitry, sa a total of 13 external interrupt request lines
are available. These 13 interrupt request lines plus the Weitek
interrupt request line, the ten-channel check line, and the
Turbo/Non-Turbo line are scanned in through one pin on the
VL82C481. Two external 74LS166s are required for scanning in these 16
signals.
The interval timer includes one 82C54 counter/timer megacell. the
counter/timer has three independent 16-bit counters and six
programmable counter modes.
the two DMA controllers are 82C37A compatible. Each controls data
transfers bet- ween an I/O channel and on- or off-board memory. The
DMA controllers can transfer data over the full 64 MB range
available. Internal latches are provided for latc- hing the middle
address bits output by the 82C37A megacells on the data bus. The
74LS612 memory mappers are integrated to generate the upper address
bits.
The VL82C481 can be programmed for asynchronous or synchronous
operation of the ISA bus.
The VL82C481 also performs all the data buffer control functions
required for a 486-based ISA bus system. Under the control of the CPU,
the VL82C481 routes data to and from the CPU's local D bus, the
internal XD bus, and the slots (SD bus). During CPU ISA bus reads,
the data is latched for synchronization with the CPU. Parity is
checked for D bus DRAM read operations. On power-on default, the chip
does not generate parity for CPU writes to DRAM, but does generate
cache write- back cycles. However, a mode is provided in which the
VL82C481 will generate parity during either CPU writes or VL master
writes. Even parity is generated and checked.
***differences to the VL82C480:...
***Configurations:...
***Features:...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?
***Info:...
***Versions:...
***Features:...
**VL82C114 Combination I/O chip ?...
**Video: ...
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**Other:...
**Not sure if they actually exist...
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