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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf
Information taken from:
1995_Intel_Pentium_Processors_and_Related_Components.pdf*
8249x Cache controllers.pdf**
>* Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95
The info and features section have been solely sourced from the first
source. The second source provides far more detail. Additional
information in the configurations section has been sourced from the
second.
Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.
***Info:...
***Configurations:...
***Features:...
**
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**VL82C113 SCAMP Combination I/O chip ?
***Info:
The VL82C113/VL82C113A SCAMP Combination I/O chip, when used with VLSI
SCAMP chips, allows designers to implement a very cost-effective
minimum chip count motherboard. This chip combines a keyboard
controller and a real-time clock with the address registers/buffers
and buffers which are normally required in PC/AT-compatible systems.
The VL82C113/VL82C113A features an AT-compatible keyboard controller
with integrated PS/2 mouse support and a 146818A-compatible real-time
clock. In addition, the VL82C113/VL82C113A has 64 additional bytes of
battery-backed CMOS RAM for use in extended system setup.
***Versions:...
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**VL82C114 Combination I/O chip ?...
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