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**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
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**SL82C550 'Rossini' Pentium [no datasheet] c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
The Symphony "Rossini" Chipset (Symphony Labs: 10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates with up to 66 MHz external clock rates, up to two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache, EDO RAM, and does dual-port busmastering IDE. It will,
apparently, adjust the voltages to its various (CPU, PCI, cache, RAM)
buses to suit their requirements, and will control up to six PCI
masters. It consists of the SL82C551 cache/memory controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.
***Configurations:...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
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**VL82C530 Eagle Ð c95
***Notes:...
***Info:...
***Configurations:...
***Features:...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
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**Not sure if they actually exist...
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