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*_IBM...
*ACC Micro...
*ALD...
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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98
***Info:...
***Configurations:...
***Features:...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82CPCPM-QC AT 16 MHz 0/1 ws [no datasheet] c88
***Notes:...
**VL82CPCAT-16QC/-20QC AT 16 MHz or 20 MHz, 0/1 ws +386SX c89...
**VL82CPCPM-16QC/-20QC AT 16 MHz or 20 MHz, Page-Mode +386SX c89...
**VL82C031/032/033 PS/2 Model 30-compatible chip set c88...
**VL82C286-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C386-SET TOPCAT 386DX PC/AT-Compatible Chip Set ?...
**VL82C386sx-SET TOPCAT 286/386SX PC/AT-Compatible Chip Set ?...
**VL82C310 SCAMP-LT ?...
**VL82C311 SCAMP-DT ?...
**VL82C311L SCAMP-DT 286 ?...
**VL82C312 SCAMP Power Management Unit (PMU) ?...
**VL82C315A SCAMP II, Low-Power Notebook Chipset ?...
**VL82C322A SCAMP II, Power Management Unit (PMU) ?...
**VL82C316 SCAMP II, PC/AT-Compatible System Controller ?...
**VL82C323 SCAMP II, 5 Volt Power Management Unit (PMU) ?...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?
***Info:
The VL82C520 Lynx/M chipset is VLSI's system solution optimized for
the expanding mobile Pentium market. Carrying forward VLSI's mobile
strategy and leveraging successful desktop innovations to offer a
complete solution, Lynx/M leaps forward and integrates the system
controller into a single Ball Grid Array (BGA) package. Included in
the Lynx/M solution is a PCI "Super I/O" controller that integrates
all the standard mobile peripherals. The Lynx/M offers a total
solution compatible with the Common Architecture industry standard
implementing highly efficient DDMA (Distributed DMA), Serial IRQ, and
features for primary PCI hot docking using a Common Architecture
compatible PCI to PCI bridge in the docking station.
Lynx/M System Controller; VL82C521
Packaged in a space-efficient low-profile 352 BGA, the Lynx/M System
Controller is the heart of the solution. BGA packaging allows
integrating functions usually partitioned into multiple packages. the
integrated functions include a 66Mhz CPU interface, 3.3V mobile PCI
2.1 compliant bus controller, 64-bit SDRAM, EDO, and FPM DRAM
controller with nine-deep fast access smart write-buffers, on-board L2
256KB write-back cache controller, and VLSI's WATTSmart power
management control. The DRAM interface provides drive for up to 24
memory devices thereby eliminating the need for external
drivers. Also, selecting SDRAM provides the opportunity to implement a
high performance system without an L2 cache.
Lynx/M Peripheral Controller; VL82C522
The Lynx/M chipset also includes a PCI Super I/O device, the Lynx/M
Mobile Peripheral Controller (MPC). This device, also packaged in a
low-profile 352 BGA, integrates a PCI 2.1 compliant bus interface, a
fully buffered Bus Mastering IDE controller, an '077 floppy disk
controller, Enhanced Capabilities Port (ECP), two 16550 UARTs with
modem functionality, an SMB/I2C bus, an IrDA 1.1 compatible Fast
Infrared communications port with ASK functionality, a Real-Time
Clock, two pulse-width modulator outputs (PWM), and a 33MHz 8052
microcontroller. Two on-board PLLs with buffering provide all the
required system clocks from only two crystal inputs, 14.318MHz and
32KHz.
A sub-ISA bus supporting 8- or 16-bit I/O or DDMA transfers, and ISA
Bus Mastering supports audio devices. Additionally, eight positive PCI
address decodes provide support to Sub-ISA peripherals.
The 8052 provides the keyboard controller functionality with built-in
scan for matrix keyboards and system boot controller functionality to
completely wake up any part or all of the system from any level of
suspend. The wake-up event can be a system event, timer, or any key
depression on the keyboard. The MPC also provides up to 25 GPIO pins
with expansion capabilities to provide flexible control of system
components.
Singular ROM architecture enabled by the integrated 8052 keyboard
controller saves both PCB space and cost by permitting a solitary ROM,
Flash, or SRAM device to be used for keyboard, graphics and system
BIOS.
WATTSMART Power Management
Incorporated in the Lynx/M chipset, the WATTSmart is a System
Management Mode-based power management system. WATTSmart includes
multiple system event monitoring, a watchdog timer, System Management
Interrupt (SMI) generation, multiple I/O traps, CPU Stop Clock
control, and provides three general purpose system Management I/O pins
(SMIOs) for control and monitoring of external devices.
Virtually all activity resources are available as speed up events and
to generate SMIs. SMIs can be generated by activity or after a period
of inactivity. An SMI that is generated from activity is generally for
a powered-down device, and the SMM handler can restore the device to
normal operation. An SMI from activity can also be used to resume the
system, start the clocks, etc.
Background
Lynx/M incorporates functions from previous desktop and mobile
chipsets. Baselinning from proven core system blocks and modifying to
reflect new market requirements allows VLSI to meet the Time-To-Market
expectations while minimizing risk.
Utilizing high-pin count BGA packaging allows Lynx/M to reduce board
space requirements by greater than 45%. this allows room on the PCB
for additional functionality while reducing the complexity of
multi-layer system boards.
Accessing VLSI's internal fab technology allows Lynx/M a path to an
advanced 0.6um CMOS process thereby achieving a true 3.3V system
without performance trade-offs.
***Configurations:...
***Features:...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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