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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C521/522 Lynx/M ?
***Info:...
***Configurations:...
***Features:
o Support for Pentium and Pentium-class CPUs
o 64-bit wide SDRAM, EDO, and FPM DRAM controller
o Nine-deep, 64-bit fast-access smart write buffers
o Fully PCI 2.1 compliant, 33MHz, synchronous or asynchronous, high
performance (120 MB/s) PCI bus with full concurrency to support
high bandwidth multi-media
o Flexible L2 write-back cache controller supporting 3-1-1-1-1-1-1-1
burst cycles
o Highly integrated chipset in low-profile BGA packages
o Active thermal feedback (ATF) for closed-loop thermal control of
the CPU
o PCI bridge support for high-performance primary PCI hot docking
o Common Architecture Serial Bus minimizes docking connector pin
count
o SMB/I2C system management bus improves battery monitoring
o Singular ROM for keyboard, System and graphics BIOS
o Full 2 channel Bus Mastering IDE controller
o Integrated '077 FDC
o Two 16550 UARTs
o 8052 keyboard controller with built-in scan for matrix keyboards and
boot controller functionality
o system clocks from power-managed PLLs with on-board buffering for
distribution
o Two PWMs to provide LCD backlight and contrast control
o Parallel port with PS2, EPP and ECP extensions
o Built-in IrDA 1.1 Fast Infrared communications port
o Multiple VCC rails and on-board level shifters to provide inder-
pendent power-down and true 5.0 Vdc peripheral support
o Support for three PS2 ports
o Real-Time Clock with CMOS
o 25 GPIO pins with expansion
o Built-in Sub-ISA bus for 16-bit DMA ISA Master audio device
o Supports 3.3V and 0V suspend with multiple resume events, I/O
trapping, and audio 0V suspend/resume
o Bus Keeper I/Os to reduce battery drain in suspend mode
o Supports shut-down option for CPU core power during powered
suspend to maximize battery life
o Supports CPU clock division emulation to effectively reduce CPU
clock frequency
o Plug-N-Play support
o Compliant with Microsoft recommendations for Win '95
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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