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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C425         486 Cache controller                              ?
***Info:...
***Versions:...
***Features:
o   Single chip second-level cache controller optimized for use with 
    the VL82C486 System Controller
o   Look-aside architecture allows cache to be board-level option
o   Write-back architecture for increased write performance
o   Direct Map with external TAGs
o   Up to 33Mhz operation
o   Supports single motherboard designs for the following cache sizes:
    - 64 KB  (caches 8 or 16 MB DRAM)
    - 128 KB (caches 16 or 32 MB DRAM)
    - 256 KB (caches 32 or 64 MB DRAM)
    - 512 KB (caches 64 or 128 MB DRAM)
    - 1 MB   (caches 128 or 256 MB DRAM)
o   Low total cache system cost:
    - Uses commodity SRAMs for Cache Tag and Cache Data
    - 25 ns data SRAMs; 20 ns tag SRAMs at 33 MHz
o   High Performance:
    - 2-1-1-1 Burst Mode read cycles with two banks of data SRAM
    - 2-2-2-2 Burst Mode read cycles with now bank of data SRAM
    - One wait state writes on cache-hits
    - Minimum cache-miss penalty
o   Flexibility:
    - Supports 8-bit or 9-bit TAG RAM (inclusive of DIRTY bit)
    - Supports one or two banks of SRAM
o   Maintains full coherency during DMA/Master Mode Cycles
    - The VL82C425 is transparent to software, acting as a front-end 
      to system DRAM
o   Setup/sizing mode provides direct access to cache SRAMs
o   128-lead metric quad flat pack (MQFP)

**????????         Cheetah 486, PCI [no datasheet]                   ?...
**VL82C3216        Bus Expanding Controller Cache with write buffer  ?...
**VL82C521/522     Lynx/M                                            ?...
**VL82C530         Eagle Ð                                         c95...
**VL82C541/543     Lynx                                            c95...
**VL82C591/593     SuperCore 590                                   c94...
**VL82C594/596/597 Wildcat                                         c95...
**I/O Chips:
**VL82C106 Combination I/O chip                                      ?...
**VL82C107 SCAMP  Combination I/O chip                               ?...
**VL82C108 TOPCAT Combination I/O chip                               ?...
**VL82C110 Combination I/O chip                                      ?...
**VL82C113 SCAMP  Combination I/O chip                               ?...
**VL82C114 Combination I/O chip                                      ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...