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*_IBM...
*ACC Micro...
**ACC82010 AT Chip Set (286 12.5/16MHz Max) c88
***info:...
***Configurations:...
***Features:...
**ACC82020 Turbo PC/AT Chip Set (286/386SX 25MHz Max) c88...
**ACC82021 Turbo PC/AT Chip Set (286/386SX 25MHz Max) >88...
**ACC82300 386 AT Chip Set (386DX) c88...
**ACC82C100 Single-Chip PC/XT Systems-Controller c90...
**ACC83000 Model 30 Integrated Chip Set (MCA) c88...
**ACC85000/A Model 50/60 Chipset (MCA) c88...
**ACC1000 Turbo PC/XT Integrated Bus and Peripheral Ctrl. 04/02/88...
**ACC2036 Single Chip Solution 2036 (286/386SX) <Jul92...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT <Jul92...
**ACC2048 WB 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications c96...
**ACC2056 ?Pentium 3.3V Notebook [no datasheet]<Jan96...
**ACC2057 PCI Notebook/Embedded Single Chip [no datasheet]<Aug96...
**ACC2066NT 486 Notebook/Embedded Single Chip [no datasheet] ?...
**ACC2086 486 VL-based System Super Chip Soluti[no datasheet] ?...
**ACC2087 Enhanced Super Chip (486 Single Chip) <Aug96...
**ACC2089 486 PCI-based System Super Chip [no datasheet] ?...
**ACC2168/GT 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2178A 32-bit 486 Green System Single Chip [no datasheet] ?...
**ACC2268 ?486 [no datasheet] ?...
**ACC???? Maple/Maple-133 486-System-On-Chip [no datasheet] ?...
**
**Support Chips:
**ACC2016 Buffer and MUX Logic c96...
**ACC2020 Power Management Chip c92...
**ACC5500 Multifunction I/O Control Chip for PS2 Model 50/60 c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
**VL82C380 Single chip 386DX PC/AT Controller +on-chip cache ?
***Info:
VLSI Technology, Inc.'s VL82C380 is a highly integrated 32-bit
single-chip PC/AT controller with on-chip cache controller designed
for use in 386DX-based ISA systems operating at up to 40 MHz. Its
cache controller is designed with a look-aside, write- back
architecture for increased write performance as well as read
performance. Full coherency is maintained during DMA/Master Mode
cycles.
The VL82C380 is a highly integration solution. A complete system can
be implemented using only the CPU, BIOS, DRAM, VL82C380, VL82C113A
Combination I/O and 3 SSI TTL's, plus optional TAG and Data SRAMs.
Tag SRAMs can be either 8- or 9-bit (7- or 8-bit tag plus a dirty
bit). Dirty and Valid bits are optional, each may be disabled in order
to increase cacheable DRAM range. The Dirty bit, when used, indicates
that the cache has been updated but not the corresponding locations in
DRAM. The Valid bit, when used, indicates that both the cache and
corresponding DRAM locations have been updated.
Only on-board DRAM is cached, this prevents coherency issues
associated with caching system memory in the USA bus. Full coherency
is maintained during DMA/Master mode cycles, so flushing and
invalidating operations are unnecessary. set-up/sizing mode
(programmable) provides direct access to the cache data SRAMs.
The Memory Controller logic is capable of accessing up to 64 MB. There
can be up to 4 banks of 256K, 1M, or 4M DRAMs used in the system. The
VL82C380 can drive two banks without external buffering. Built-in
page-mode operations and up to 2-way interleaving allow the PC
designer to maximize system performance using low-cost
DRAMs. Programmable DRAM timing is provided for RAS precharge, RAS to
CAS delay, and CAS pulse width.
***Configuration:...
***Features:...
**VL82C325 VL82C386SX System Cache controller ?...
**VL82C335 VL82C386DX System Cache ctrl. [no d.sheet] ?
***Notes:...
**VL82C315A/322A/3216 Kodiak 32-Bit Low-Voltage Chip Set ?...
**VL82C420/144/146 SCAMP IV [no datasheet, some info] c93...
**VL82C480 System/Cache/ISA bus Controller ?...
**VL82C481 System/Cache/ISA bus Controller c92...
**VL82C486 Single-Chip 486, SC486, Controller ?...
**VL82C425 486 Cache controller ?...
**???????? Cheetah 486, PCI [no datasheet] ?...
**VL82C3216 Bus Expanding Controller Cache with write buffer ?...
**VL82C521/522 Lynx/M ?...
**VL82C530 Eagle Ð c95...
**VL82C541/543 Lynx c95...
**VL82C591/593 SuperCore 590 c94...
**VL82C594/596/597 Wildcat c95...
**I/O Chips:
**VL82C106 Combination I/O chip ?...
**VL82C107 SCAMP Combination I/O chip ?...
**VL82C108 TOPCAT Combination I/O chip ?...
**VL82C110 Combination I/O chip ?...
**VL82C113 SCAMP Combination I/O chip ?...
**VL82C114 Combination I/O chip ?...
**Video: ...
**Disk:...
**Modems:...
**Other:...
**Not sure if they actually exist...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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