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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94
***Info:...
***Versions:...
***Features:
o   VL to PCI Bridge
    - Combined with VT82C486 or VT82C496G for 80486SX/DX/DX2/DX4 based 
      PCI/VL/ISA Green-PC systems
    - Combined with VT82C530MV chip set for Pentium/P54C/M1 based 
      PCI/VL/ISA Green-PC Systems
o   Sophisticated Bridging Capabilities
    - Supports PCI master to PCI slave cycles
    - Supports PCI master to VL bus slave, system memory and ISA 
      slave cycles
    - Supports VL master including CPU to PCI slave cycles
    - Supports ISA master to VL or PCI slave cycles
    - Supports multiple accelerated decoding schemes from VL master 
      including CPU to PCI and ISA slaves
    - Supports CPUs with write-back level-one cache
    - Concurrent CPU and PCI operation
    - 4 level of CPU/VL to PCI post write buffers
    - Automatic detection of data streaming burst cycles from CPU/VL 
      to PCI bus
    - 4 level of post write buffers from PCI master to VL slave, 
      system memory and ISA slaves
    - 4 level of prefetch buffers from system memory for access by PCI 
      masters
    - Bursting capability for both PCI and CPU/VL bus
o   Intelligent PCI Interface
    - PCI 2.0 compliant
    - Synchronous or divide-by-two CPU clock
    - Hidden arbitration for up to four PCI masters
    - Supports PCI preemption and time-out function
    - Supports PCI master and slave initiated abort mechanism
    - Supports PCI lock function
    - Supports data parity generation for PCI master read cycles
    - Supports data parity checking for PCI master write cycles
    - Supports parity error and system error reporting on the PCI bus
    - Supports PCI configuration cycles
    - Interrupt steering and conversion to edge triggering for ISA 
      compatibility
o   PCI Compliant IO Characteristics
o   0.8um high speed and low power CMOS process
o   160pin PQFP package

**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
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