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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*OPTi...
**82c463         SCNB Single Ship Notebook                        c:92
***Info:...
***Configurations:...
***Features:...
**82c465MV/A/B   Single-Chip Mixed Voltage Notebook Solution    <Oct97...
**82C481?/482?   HiP/486 & HiB/486 [no datasheet]                Oct89...
**82C491/392     486WB PC/AT Chipset                         <04/21/91...
**82C493/392     486SXWB                                     <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet]                   ?...
**82C495SLC      DXSLC 386/486 Low Cost Write Back                c:92...
**82C495XLC      PC/AT Chip Set                                   c:93...
**82c496A/B      DXBB PC/AT Chipset                             <Mar92...
**82C496/7       DXBB PC/AT Chipset (Cached)                 <01/16/92...
**82C498         DXWB PC/AT chipset [no datasheet]                   ?...
**82C499         DXSC DX System Controller                        c:93...
**82C546/547     Python PTM3V                                     c:94...
**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT8501       Apollo MVP4,Single-Chip 66-100MHz & AGP       <11/04/98
***Notes:...
***info:
The  Apollo MVP4  is  a PC  Socket-7  system logic  North Bridge  with
integrated 2D  / 3D Graphics  accelerator.  The core logic  portion of
the chip is  based on the popular 100MHz VIA  Apollo MVP3 chipset with
enhanced features  and graphics accelerator based  on the Cyber9398DVD
from Trident  Microsystems, Inc.  The  combination of the  two leading
edge  technologies   provides  a  stable,   cost-effective,  and  high
performance solution for personal computers, embedded systems, set-top
boxes and  others.  As  shown in Figure  1 [see datasheet]  below, the
Apollo MVP4 will interface to:

o Socket 7 CPU (66 – 100 MHz)
o L2 Cache RAM & Tag
o SDRAM Memory Interface
o PCI Bus (30 - 33 MHz)
o Analog RGB Monitor with DDC
o DFP / Digital Monitor Interface (TMDS)
o Video Capture / Playback CODECs

Apollo MVP4 Core Logic Overview
The Apollo  MVP4 –  System Media Accelerated  North Bridge (SMA)  is a
high performance, cost-effective and energy efficient solution for the
implementation  of Integrated  2D/3D  Graphics -  PCI  - ISA  personal
computer  systems from  66 MHz  to 100  MHz based  on  64-bit Socket-7
(Intel Pentium and Pentium MMX; AMD K6 and K6-2; Cyrix / National 6x86
/ 6x86MX, IDT / Centaur C6/WinChip), and Rise MP6 processors.

The Apollo  MVP4 controller provides superior  performance between the
integrated  2D/3D Graphics  Engine, CPU,  optional  synchronous cache,
DRAM,  and PCI bus  with pipelined,  burst, and  concurrent operation.
For  L2-Cache  solutions  using  pipelined  burst  synchronous  SRAMs,
3-1-1-1-1-1-1-1  timing  can  be  achieved  for both  read  and  write
transactions at 100 MHz.  Tag timing is specially optimized internally
(less  than 4 nsec  setup time)  to allow  implementation of  L2 cache
using an external tag for t  he most flexible cache organization (0K /
256K / 512K / 1M /  2M).  Four cache lines (16 quadwords) of CPU/cache
to  DRAM  write  buffers  with concurrent  write-back  capability  are
included on chip to speed up cache read and write miss cycles.

The Apollo  MVP4 supports six  banks of DRAMs  up to 768MB.   The DRAM
controller  supports  standard Fast  Page  Mode  (FP) DRAM,  EDO-DRAM,
Synchronous DRAM  (SDRAM), and Virtual  Channel Synchronous DRAM  in a
flexible mix  / match manner.   The Synchronous DRAM  interface allows
zero wait state bursting between the  DRAM and the data buffers at 100
MHz.  The six banks of DRAM can be composed of an arbitrary mixture of
1M / 2M  / 4M / 8M  / 16MxN DRAMs.  The DRAM  controller also supports
optional ECC (single-bit error  correction and multi-bit detection) or
EC (error checking) capability separately selectable on a bank-by-bank
basis.   The  DRAM Controller  can  run at  either  the  host CPU  bus
frequency (66  / 100 MHz) or  at the PC100 memory  frequency (100 MHz)
with  built-in deskew  PLL  timing control.   With  the advanced  DRAM
controller,  the  Apollo  MVP4   allows  implementation  of  the  most
flexible, reliable, and high-performance DRAM interface.

The  Apollo MVP4  also  supports  full AGP  v2.0  capability with  the
internal 2D/3D Graphics Engine for maximum software compatibility.  An
eight level request  queue plus a four level  post-write request queue
with thirty-two  and sixteen quadwords  of read and write  data FIFO’s
respectively   are  included   for  deep   pipelined  and   split  AGP
transactions.   A  single-level  GART  TLB with  16  full  associative
entries and  flexible CPU/AGP/PCI  remapping control is  also provided
for  operation  under  protected  mode operating  environments.   Both
Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.

The Apollo MVP4 supports one 32-bit  3.3 / 5V system bus (PCI) that is
synchronous  /  pseudo-synchronous to  the  CPU  bus.   The chip  also
contains a built-in AGP bus  -to- PCI bus bridge to allow simultaneous
concurrent  operations  on each  bus.   Five  levels (doublewords)  of
posted write buffers are included  to allow for concurrent CPU and PCI
operation.  For PCI master operation, forty-eight levels (doublewords)
of posted  write buffers and sixteen levels  (doublewords) of prefetch
buffers are  included for concurrent PCI bus  and DRAM/cache accesses.
The   chip  also   supports  enhanced   PCI  bus   commands   such  as
Memory-Read-Line,   Memory-Read-Multiple,   and   Memory-Write-Invalid
commands to  minimize snoop overhead.  In  addition, advanced features
are  supported such  as snoop  ahead, snoop  filtering,  L1 write-back
forward to  PCI master, and L1  write-back merged with  PCI post write
buffers  to minimize  PCI master  read latency  and  DRAM utilization.
Delayed transaction  and read caching mechanisms  are also implemented
for further improvement of overall system performance.

The Apollo MVP4 provides independent  clock stop control for the CPU /
SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of
the SDRAM.  A separate suspend-well plane is implemented for the SDRAM
control  signals  for  Suspend-to-DRAM  operation.  Coupled  with  the
324-pin Ball Grid Array VIA VT82C596B south bridge chip, a complete PC
main board can be implemented with no external TTLs.

The Apollo MVP4 controller  coupled with VIA’s highly integrated south
bridge,  the   VT82C686A,  is  ideal  for   high  performance,  energy
efficient,  and  highly integrated  computer  systems.  The  VT82C686A
supports a PCI-to-ISA bus  controller, four USB ports, dual bus-master
IDE  with UltraDMA33/66,  AC97  basic digital  audio, system  hardware
monitoring, and integrated "Super-I/O" functionality.
***Configurations:...
***Features:...
**VT82C680     Apollo P6, Pentium-Pro Chip Set               <08/30/96...
**Support chips:
**VT82C505     Pentium/486 VL to PCI Bridge                  <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller          <10/13/96...
**VT82C596/A   Mobile PCI Integrated Peripheral Controller   <11/05/97...
**VT82C686A/B  PCI Super-I/O Integrated Peripheral Ctrl.     <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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*Western Digital...
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