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**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**GCK181 Universal PS/2 Chip Set c:Mar89
***Info:...
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
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*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
**SL9XXX FlexSet family General information
The SL9XXX series seems to have been designed to work with the 80286,
80386SX and 80386DX, and is possibly compatible with the 80486. What-
ever CPU used, the chipset contains the following chips, known as the
"Core AT Logic chips":
SL9011 System Controller
SL9020 Data Controller (2x for 32bit 386DX)
SL9025 Address Controller
SL9030 Integrated Peripheral Controller
The memory controller is then selected based on the CPU. It appears
that the lineup originally consisted of the following chips, known as
"Personalized AT Logic":
SL9151 Page Interleave Memory (80286)
SL9250 Memory Controller (80386SX)
SL9350 Page Mode Memory Controller (80386DX)
Later updates were:
SL9251 Page Interleave Memory Controller (80386SX)
SL9351 Page Interleave Memory Controller (80386DX)
Further updates were:
SL9252 System and Memory Controller (80386SX)
SL9352 System and Memory Controller (80386DX)
As far as i can tell, these chips only require the addition of the
SL9020, or 2x in the case of the SL9352. The datasheets are quite
terse.
These parts and the whole design of the datasheets are very similar to
the chipsets released by Logicstar. I, however, cannot find any record
of a link between the companies. See *Logicstar for details.
**SL9011 System Controller (80286/80386SX/DX, 16/20/25MHz) <Jan90...
**SL9020 Data Controller <Jan90...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97
***Info:
The VT82C590 Apollo-VP2 is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
Pentium/AMD5K86/AMD6K86/Cyrix6X86 super-scalar processors.
The Apollo-VP2 chip set consists of the VT82C595 system controller
(328 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
VT82C595 system controller provides superior performance between the
CPU, optional synchronous cache, DRAM and the PCI bus with pipelined,
burst and concurrent operation. For pipelined burst synchronous SRAMs,
3-1-1-1-1-1-1-1 timing can be achieved for both read and write
transactions at 66 Mhz. Four cache lines (16 quadwords) of CPU/cache
to DRAM write buffers with concurrent write-back capability are
included in the chip to speed up the cache read and write miss cycles.
The VT82C595 supports six banks of DRAMs up to 512KB. The DRAM
controller supports Standard Page Mode DRAM, EDO DRAM and Synchronous
DRAM in a flexible mix / match manner. The Synchronous DRAM interface
allows zero wait state bursting between the DRAM and the data buffers
at 66Mhz. The six banks of DRAM can be composed of an arbitrary
mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. Each bank may be populated
with either 32bit or 64bit data width. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit
detection) capability.
The VT82C595 supports 3.3 / 5V 32-bit PCI bus with 64-bit to 32-bit
data conversion. Five levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. Consecutive
CPU addresses are converted into burst PCI cycles with byte merging
capability for optimal CPU to PCI throughput. For PCI master
operation, forty-eight levels (doublewords) of post write buffers and
sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chipset also supports
enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-
Multiple and Memory-Write-Invalid commands to minimize snoop
overhead. In addition, the chipset supports advanced features such as
snoop ahead, snoop filtering, L1 write-back forward to PCI master and
L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. The VT82C586B PCI to ISA
bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization
and (PCI-2.1 compliant). The VT82C586B also includes an integrated
keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 256 byte CMOS RAM, integrated master
mode enhanced IDE controller with full scatter and gather capability
and extension to UltraDMA-33 / ATA-33 for 33MB/sec transfer rate,
integrated USB interface with root hub and two function ports with
built-in physical layer transceivers, Distributed DMA support, and
OnNow / ACPI compliant advanced configuration and power management
interface. A complete main board can be implemented with only six
TTLs.
The VT82C590 chipset is ideal for high performance, high quality, high
energy efficient and high integration desktop and notebook PCI/ISA
computer systems.
***Configurations:...
***Features:...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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