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**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C291 SXWB PC/AT Chipset (386SX) c:91
***Info:...
***Configurations:...
***Features:...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97
***Info:
The VT82C590 Apollo-VP2 is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
Pentium/AMD5K86/AMD6K86/Cyrix6X86 super-scalar processors.
The Apollo-VP2 chip set consists of the VT82C595 system controller
(328 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The
VT82C595 system controller provides superior performance between the
CPU, optional synchronous cache, DRAM and the PCI bus with pipelined,
burst and concurrent operation. For pipelined burst synchronous SRAMs,
3-1-1-1-1-1-1-1 timing can be achieved for both read and write
transactions at 66 Mhz. Four cache lines (16 quadwords) of CPU/cache
to DRAM write buffers with concurrent write-back capability are
included in the chip to speed up the cache read and write miss cycles.
The VT82C595 supports six banks of DRAMs up to 512KB. The DRAM
controller supports Standard Page Mode DRAM, EDO DRAM and Synchronous
DRAM in a flexible mix / match manner. The Synchronous DRAM interface
allows zero wait state bursting between the DRAM and the data buffers
at 66Mhz. The six banks of DRAM can be composed of an arbitrary
mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. Each bank may be populated
with either 32bit or 64bit data width. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit
detection) capability.
The VT82C595 supports 3.3 / 5V 32-bit PCI bus with 64-bit to 32-bit
data conversion. Five levels (doublewords) of post write buffers are
included to allow for concurrent CPU and PCI operation. Consecutive
CPU addresses are converted into burst PCI cycles with byte merging
capability for optimal CPU to PCI throughput. For PCI master
operation, forty-eight levels (doublewords) of post write buffers and
sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chipset also supports
enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-
Multiple and Memory-Write-Invalid commands to minimize snoop
overhead. In addition, the chipset supports advanced features such as
snoop ahead, snoop filtering, L1 write-back forward to PCI master and
L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. The VT82C586B PCI to ISA
bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization
and (PCI-2.1 compliant). The VT82C586B also includes an integrated
keyboard controller with PS2 mouse support, integrated DS12885 style
real time clock with extended 256 byte CMOS RAM, integrated master
mode enhanced IDE controller with full scatter and gather capability
and extension to UltraDMA-33 / ATA-33 for 33MB/sec transfer rate,
integrated USB interface with root hub and two function ports with
built-in physical layer transceivers, Distributed DMA support, and
OnNow / ACPI compliant advanced configuration and power management
interface. A complete main board can be implemented with only six
TTLs.
The VT82C590 chipset is ideal for high performance, high quality, high
energy efficient and high integration desktop and notebook PCI/ISA
computer systems.
***Configurations:...
***Features:...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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