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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*Unresearched:...
*VIA...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97
***Notes:...
***Info:
The VT82C580VPX Apollo-VPX is a high performance, cost-effective and
energy efficient chip set for implementation of PCI / ISA desktop and
notebook personal computer systems based on 64-bit P54C/
Pentium/K5/K6/M1 super-scalar processors. The CPU / cache connection
is supported using an "asynchronous" interface up to 75Mhz CPU
external bus speed (with CPU internal speed up to 200Mhz and above),
with CPUs such as the "P200+" processors from Cyrix / IBM
Microelectronics. The "asynchronous" interface allows the processor
external bus frequency to be increased above 66MHz while still
allowing the PCI bus to run at the specified top frequency of 33MHz.
The chipset also supports CPU external bus speeds up to 66MHz in
"synchronous" mode, so may also be used in boards designed around the
popular VT82C580VP (Apollo VP) chipset. The 66MHz external bus speed
is used primarily for Intel and AMD processors. The CPU, DRAM and PCI
bus are all independently powered so that each of the bus can be run
at 3.3v or 5v, independently. The ISA bus always runs at 5v.
The VT82C580VPX chip set consists of the VT82C585VPX system
controller, the VT82C586B PCI to ISA bridge, and two instances of the
VT82C587VP data buffers. The VT82C585VPX is the only different
component in a VPX-based system from the chips used in an Apollo VP
system: the same VT82C586B South Bridge chip may be used with all VIA
North Bridge chips (Pentium and PentiumPro-based designs) and the
VT82C587VP Data Buffer is the same chip as is used in Apollo VP
designs.
The CPU bus is minimally loaded with only the CPU, secondary cache and
the chip set. The VT82C587VP data buffers isolate the CPU bus from
the DRAM and PCI bus so that CPU and cache operation may run reliably
at the high frequencies demanded by today's processors. The
VT82C585VPX contains multiple deep FIFOs to allow efficient concurrent
operation and DRAM utilization. The VT82C586B PCI to ISA bridge
includes integrated 206-style IPC (DMA, interrupt controller and
timer), integrated keyboard controller with PS2 mouse support,
integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, ACPI-compatible Power Management subsystem, integrated master
mode enhanced IDE / UltraDMA-33 disk controller with full scatter and
gather capability, and integrated USB (universal serial bus) interface
with root hub and two function ports with built-in physical layer
transceivers (refer to the separate VT82C586B Data Sheet for
additional information). A complete main board can be implemented
with only six TTLs. Refer to Figure 1 [see datasheet] for the system
block diagram.
***Configurations:...
***Features:...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
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