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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory bus controller, provide a second-level
cache subsystem that eliminates the memory latency and bandwidth
bottleneck for a wide range of multiprocessor systems based on the
i860 XP microprocessor. The CPU interface is optimized to serve the
i860 XP microprocessor with zero wait states at up to 50 MHz. A
secondary cache built from the 82495XP and 82490XP isolates the CPU
from the memory subsystem; the memory can run slower and follow a
different protocol than the i860 XP microprocessor.
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88
***Info:...
***Versions:...
***Features:...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95
***Info:...
***Configurations:...
***Features:
o PCI/ISA Green PC Ready
o High Integration
- VT82C575M system controller
- VT82C576M PCI bus controller
- Two instances of the VT82C577M data buffers
- Glueless interface to the VT82C416 integrated clock generator,
real time clock with extended CMOS, plug and play control and
keyboard controller with PS/2 mouse support
- Ten TTLs for a complete main board implementation
o Flexible CPU Interface
- 64-bit P54C, Pentium, K5 and M1 CPU interface
- 3.3v or 5v CPU and cache interface
- CPU external bus speed up to 66Mhz (internal 150Mhz and above)
- Supports CPU internal write-back cache
- Concurrent CPU/cache and PCI/DRAM operation
- System management interrupt, memory remap and STPCLK mechanism
- Cyrix M1 linear burst support
- CPU NA#/Address pipeline capability
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Burst Synchronous (Pipelined or non-pipelined), asynchronous
SRAM and Cache Module support
- Eight-pin CWE# and GWE# control options
- Flexible cache size: 0K/128K/256K/512K/1M/2MB
- 32 byte line size to match the primary cache
- Integrated 10-bit tag comparator
- Interleaved SRAM access
- 3-1-1-1 read/write timing for Burst Synchronous SRAM access
at 66Mhz
- 3-2-2-2 (read) and 4-2-2-2 (write) timing for interleaved
asynchronous SRAM access at 66Mhz
- Data streaming for simultaneous primary and secondary cache
line fill
- System and video BIOS cacheable and write-protect
- Programmable cacheable region and cache timing
- Optional combined tag and alter bit SRAM for write-back scheme
o Fast DRAM Controller
- Concurrent DRAM Writeback
- Four levels of CPU/cache to DRAM write buffer
- Standard Page Mode/EDO/Burst EDO-DRAM support in a flexible/
mixed combination
- EDO-DRAM auto-detect
- Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs
- 8 banks up to 512MB DRAMs
- Flexible row and column addresses
- 64 bit or 32 bit data width
- Burst read and write operation
- Programmable DRAM timing
- BIOS shadow at 16KB increment
- System management memory remapping
- Decoupled and burst DRAM refresh with staggered RAS timing
- CAS-before-RAS refresh timing
o Intelligent PCI Bus Controller
- 32 bit PCI interface
- PCI Master snoop ahead and snoop filtering
- Concurrent PCI master/CPU/IDE operations
- Synchronous Bus to CPU clock with divide-by-two from the CPU
clock
- Multiple accelerated schemes for high bus throughput
- Automatic detection of data streaming burst cycles from CPU to
the PCI bus
- Four level of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- PCI to system memory data streaming up to 110Mbyte/sec
- Four level of post write buffers from PCI masters to DRAM
- Four level of prefetch buffers from DRAM for access by PCI
masters
- Zero wait state PCI master and slave burst transfer rate
- Complete steerable PCI interrupts
- IDE and ISA bus through peer PCI bus to avoid slower traffic
blocking the regular PCI bus
- PCI-2.1 compliant
o Enhanced Master Mode PCI IDE Controller
- Dual channel master mode PCI supports four Enhanced IDE devices
- Mode 4 and Mode 5 transfer rate up to 22MB/sec
- Sixteen doubleword of prefetch and write buffers
- Interlaced commands between two channels
- Separate IDE data bus and control signals from the PCI and ISA
bus to reduce loading and to enhance performance
- Bus master programming interface for ATA controllers SFF-8038
rev.1.0 compliant
- Full scatter and gather capability
- Support ATAPI compliant devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
o Plug and Play Controller
- Dual interrupt and DMA signal steering with plug and play control
- Two programmable chip selects
- Microsoft Windows 95TM and plug and play BIOS compliant
o Sophisticated Power Management Unit
- Normal, doze, sleep, suspend and conserve modes
- System event monitoring with two event classes
- One idle timer, one peripheral timer and one general purpose
timer
- More than ten general purpose Input/Output ports
- Six external event input ports with programmable SMI condition
- Complete leakage control when external component is in power off
state
- Primary and secondary interrupt differentiation for individual
channels
- Clock stretching, clock throttling and clock stop control
- Multiple internal and external SMI sources for flexible power
management models
- APM 1.1 compliant
o Synchronous ISA Bus Controller
- Synchronous ISA bus clock
- Programmable wait state, command delay and IO recovery time
- Bus conversion and data alignment
- Hardware and software de-turbo control
- Fast reset and Gate A20 operation
- Integrated 82C206 peripheral controller
- Edge trigger or level sensitive interrupt
- Flash EPROM and combined BIOS support
o Built-in nand-tree pin scan test capability
o 0.6um mixed voltage, high speed and low power CMOS process
o 208 pin PQFP for VT82C575M
o 208 pin PQFP for VT82C576M
o 100 pin PQFP for VT82C577M
o 100 pin PQFP for VT82C416
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
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