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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**????? (Profusion) c:99
Chips:
Memory Access Controller (MAC)
Data Interface Buffer (DIB)
CPUs: 8x P-III Xeon Oct
DRAM Types: SDRAM PC100 2-way Interleave dual channel
Max Mem: 32GB
ECC/Parity: ECC
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3 PCI-66/64
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:...
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94
***Info:...
***Configurations:...
***Features
1. Fully IBM PC/AT Compatible
2. Flexible CPU and Local Bus Interface
- Supports 80486SX/DX/DX2/DX4 and compatible CPUs
- CPU speed up to 100 Mhz including 80486DX-50, 80486DX2-66 and
80486DX4-100
- Supports CPUs with write-back internal cache, e.g. P24D, P24T
and Cx486DX/DX2
- Snoop filtering for write-back CPUs
- Supports SMI protocols of Intel, AMD, TI and Cyrix CPUs
- CPU clock stretching and throttling
- Zero frequency and zero voltage CPU suspend
- Soft and hard CPU reset
- Direct VESA and other local bus interface with DMA/master access
- Built-in arbitration for two local bus masters
3. Advanced Cache Controller
- Write back/write through scheme
- Direct map scheme
- Flexible cache size: 0K/32K/64K/128K/256K/512K/1MB
- One bank or two banks of data independent of cache size
- Integrated 8-bit tag comparator
- Interleaved SRAM access to achieve 2-1-1-1 burst fill
- Supports burst read and burst write transfers
- System and video BIOS cacheable and write-protect
- Programmable cache timing
- Programmable non-cacheable region
- Optional combined tag and alter bit SRAM for the write-back
scheme
- Eight bit tag under the combined tag-alter scheme without
sacrifice of cacheable space
4. Fast Page Mode DRAM Controller
- Mixed 256K/512K/1M/2M/4M/8M/16MxN DRAMs
- 8 banks up to 128MB
- Flexible column and row addresses
- 30 pin (x9) and single/double density 72 pin (x36) SIMM
module support
- Programmable DRAM timing
- BIOS shadow at 16KB increment
- 256/384K memory relocation
- System management memory remapping
- Decoupled DRAM refresh with staggered RAS timing
- CAS-before-RAS and slow refresh
5. Synchronous ISA Bus Controller
- Synchronous ISA bus clock
- Programmable wait state, command delay and IO recovery time
- Bus conversion and data alignment
- Hardware and software de-turbo control
- Fast reset and Gate A20 operation
- Integrated 82C206 peripheral controller
- Edge trigger or level sensitive interrupt controller
- Flash EPROM and combined BIOS support
6. Integrated Power Management Unit
- Normal, conserve, doze, sleep and suspend modes
- System event monitoring with two event classes and two idle
timers
- Primary and secondary interrupt differentiation for individual
channels
- One extended peripheral timer and one general purpose timer
- Automatic conserve mode operation for short and frequent system
idleness
- Modular clock and modular power
- CPU clock stretching, throttling or stop without affecting the
ISA bus clock
- Zero frequency operation with automatic resume
- Zero volt operation with leakage control
- Four general purpose IO or power control ports
- APM 1.1 compliant
7. Integrated Local Bus IDE Controller
- 32-bit host data transfer
- Mode-3 transfer capabilities (>10MB/s)
- Programmable read/write, master/slave and active/recovery timing
in units of CPU clock
- Prefetch and write buffers
- Support either primary (1F0-1F7h) or secondary (170-177h)
channel with two devices
- No external logic required
8. High Integration and Complete Functionality
- Glueless interface with the VT82C406MV IXP (Integrated X-bus
Peripheral Controller, 100PQFP) to eliminate the multi-clock
generator, the keyboard controller with PS2 mouse, the DS-1285
style real time clock with extended CMOS RAM and the address
buffers.
- 9 TTLs for a complete main board implementation
- Optional VT82C505 (160 PQFP) to bridge a VL/ISA system to the
PCI bus
9. 0.8um high speed and low power CMOS process
10. 208-pin PQFP package
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94
***Configurations:...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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