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**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:...
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**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL82C550   'Rossini' Pentium          [no datasheet]            c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html

The Symphony  "Rossini" Chipset  (Symphony Labs:  10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates  with up  to 66  MHz external  clock rates,  up to  two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache,  EDO RAM, and  does dual-port busmastering IDE.   It will,
apparently, adjust the voltages to  its various (CPU, PCI, cache, RAM)
buses  to suit  their requirements,  and will  control up  to six  PCI
masters.   It consists  of the  SL82C551 cache/memory  controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.

***Configurations:...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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