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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88
***Info:...
***Versions:...
***Features:...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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*UMC...
**UM82C206     Integrated Peripheral Controller                    <91
***Info:
The UM82C206  Integrated Peripheral  controller includes two  8237 DMA
controllers, two  8259 Interrupt controllers, one  8254 Timer/Counter,
one MC146818 compatible  Real Time Clock, an additional  64 bytes CMOS
RAM,  one  74LS612   memory  mapper,  and  some   top  level  decoder/
configuration logic circuits.  It is a single chip  integration of all
main peripheral  parts attached  to the X  bus of  PC/AT architecture.
While  providing  full  compatibility  with  PC/AT  architecture,  the
UM82C206  also  offers  some  enhanced  features  and  improved  speed
performance. These  include an additional  64 bytes of  user definable
CMOS RAM in real time clock  and drastically reduced recovery time for
the 8237, 8259  and 8254.  Programmable wait state  option is provided
for the DME  cycles and CPU I/O cycles accessing  this chip. This chip
also  provides programmable  8  or  4 MHz  DMA  clock selection.   The
UM82C206 is implemented using advanced 1.5u CMOS design technology and
is packaged in an 84-pin PLCC.

***Versions:...
***Features:...
**UM82c45x     Serial/Parallel chips                                 ?...
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