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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:
o Two-Way, Set Associative, Secondary Cache for i860 XP
Microprocessor
o 50 MHz "No Glue" Interface with CPU
o Configurable
- Cache Size 256 or 512 Kbytes
- Line Width 32, 64 or 128 Bytes
- Memory Bus Width 64 or 128 Bits
o Dual-Ported Structure Permits Simultaneous Operations on CPU and
Memory Buses
o Efficient MRU Way Prediction
- Zero Wait States on MRU Hit
- One Walt State on MRU Miss
o Dynamically Selectable Update Policies
- Write-Through
- Write-Once
- Write-Back
o MESI Cache Consistency Protocol
o Hardware Cache Snooping
o Maintains Consistency with Primary Cache via Inclusion Principle
o Flexible User-Implemented Memory Interface Enables Wide Range of
Product Differentiation
- Clocked or Strobed
- Synchronous or Asynchronous
- Plpelining
- Memory Bus Protocol
o 82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid
Array Package
o 82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack
Package
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?
***Notes:...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91
***Info:
The UM82152 is a high-performance cache controller for Intel 80386
based systems and provides high levels of integration and
functionality. It interfaces directly to the 80386; no additional
support logic is required. A complete 32-kilobyte cache can be
designed with just one UM82152 and four 8K by 8-bit static RAMs.
The UM82152 architecture enables easy design-in with current speed
versions of the 80386, and simple migration to faster version
processors with no alteration to system or memory design.
The 80386, operating in pipelined mode with the UM82152, runs with
zero wait states during a cache hit (requested data is present in
cache). If the data is not present (cache miss), it is fetched from
main memory by the UM82152. This approach yields the high-speed
performance of fast SRAMs for code and data most frequently used,
while providing design economies (such as board space savings and
lower component costs) by storing infrequently used code and data in
slower dynamic RAM (with cycle times greater than 125 nanoseconds)
that can be located in large memory banks either on-board or
off-board.
The reduced system bus traffic inherent in the UM82152 implementation
produces system performance gains by freeing the bus for use by other
devices.
***Versions:...
***Features:...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
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*ZyMOS...
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