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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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***810         (Whitney)       04/26/99...
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***815ep       (Solano-3)      c:Nov'00...
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***845         (Brookdale)     09/10/01...
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***845E        (Brookdale-E)   05/20/02...
***845G        (Brookdale-G)   05/20/02...
***845GL       (Brookdale-GL)  05/20/02...
***845GE       (Brookdale-GE)  10/07/02...
***845PE       (Brookdale-PE)  10/07/02...
***845GV       (Brookdale-GV)  10/07/02...
***848P        (Breeds Hill)   c:Aug'03...
***850         (Tehama)        11/20/00...
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***852GM       (Montara-GM)    01/14/03...
***852GMV      (Montara-GM)    ???...
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***854         (?)             04/11/05...
***855GM       (Montara-GM)    03/12/03...
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***855PM       (Odem)          03/12/03...
***860         (Colusa)        05/21/01...
***865G        (Springdale)    05/21/03...
***865PE       (Springdale-PE) 05/21/03...
***865P        (Springdale-P)  05/21/03...
***865GV       (Springdale-GV) c:Sep'03...
***875P        (Canterwood)    04/14/03...
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**UM82152      Cache Controller (AUStek A38152 clone)              <91
***Info:
The  UM82152 is a  high-performance cache  controller for  Intel 80386
based   systems  and   provides   high  levels   of  integration   and
functionality.  It interfaces  directly  to the  80386; no  additional
support  logic  is required.   A  complete  32-kilobyte  cache can  be
designed with just one UM82152 and four 8K by 8-bit static RAMs.

The  UM82152 architecture  enables easy  design-in with  current speed
versions  of  the  80386,  and  simple  migration  to  faster  version
processors with no alteration to system or memory design.

The 80386,  operating in  pipelined mode with  the UM82152,  runs with
zero  wait states during  a cache  hit (requested  data is  present in
cache). If  the data is not  present (cache miss), it  is fetched from
main  memory by  the  UM82152.  This  approach  yields the  high-speed
performance  of fast  SRAMs for  code and  data most  frequently used,
while  providing design  economies (such  as board  space  savings and
lower component costs)  by storing infrequently used code  and data in
slower  dynamic RAM (with  cycle times  greater than  125 nanoseconds)
that  can  be  located  in  large  memory  banks  either  on-board  or
off-board.

The reduced system bus  traffic inherent in the UM82152 implementation
produces system performance gains by  freeing the bus for use by other
devices.

***Versions:...
***Features:
o   Controls 32-kB, 4-way, set-associative cache
o   Available in 16-MHz, 20-MHz, and 25-MHz speeds
o   Direct interface to the 80386
o   Direct interface to industry-standard 8K x 8 SRAMs:
    45 ns for 16-MHz systems
    35 ns for 20-MHz systems
    25 ns for 25-MHz systems
o   Full 32-bit addressability for 4-GB memory support
o   Cache coherency support
o   Software cache invalidation
o   On-chip programmable noncached regions
o   Write buffer support
o   Gate A20 support
o   1.5 micron CMOS technology
o   84-lead PLCC, JEDEC standard package
o   Pin and functionally identical to A38152*

>*A38152 is Austek's cache controller for 25 MHz 386 AT system.
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
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