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**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Performance Second Level Cache
- Zero Walt States at 66 MHz
- Two-way Set Associative
- Write-Back with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor
- Chip Set Version of Pentium Processor
- Superscalar Architecture
- Enhanced Floating Point
- On-chip SK Code and SK Data Caches
- See Pentium Processor User's Manual Volume 2 for more
Information
o Highly Flexible
- 256K to 512K with parity
- 32, 64, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous, and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus, and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read-for Ownership, Write-Allocation, and Cache-to-
Cache Transfers
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**TACT83000 AT 'Tiger' Chip Set (386) c89
***Info:...
***Configurations:...
***Features:...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
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