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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*OPTi...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96
***Notes:...
***Info:
The OPTi Viper-N+ chipset is the leading solution for PCI-based mobile
applications.   Viper-N+  features   leading  edge   power  management
capability and  flexibility for Intel Pentium  75/90/100/120 and Cyrix
6x86 processor based  notebooks. The chipset incorporates desktop-like
performance features  such as L1 and  L2 cache support,  a full 64-bit
DRAM  controller  and  an  integrated  PCI  controller,  in  a  highly
integrated three chip set.

In  terms of  advanced  power  management, no  chipset  offers a  more
effective, comprehensive or flexible feature set, allowing for maximum
performance  with  minimum  power  consumption  for  extended  battery
life. In  fact, for typical applications,  Viper-N+'s power management
unit reduces power consumption by as much as 80%.

Viper-N+ offers the highest level  of system integration, enabling the
lowest  system  cost  and  real  estate  requirement  for  Pentium-PCI
notebooks.  A system without TTL is achievable with synchronous cache.
And, PCI  offers easy  upgradability to emerging  standard interfaces,
such  as  PCMCIA/CardBus  and  PCI  docking  stations.  Viper-N+  also
features an integrated local bus IDE  controller to avoid ISA data bus
bottlenecks.

OPTi coupled  its expertise in mobile technology  and PCI-based design
to create its second generation  64-bit CPU mobile chipset. The result
is  Viper-N+,  enabling  the  highest levels  of  performance,  system
integration  and  power management  capability  available for  Pentium
PCI-based mobile systems.

***Configurations:...
***Features:...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock  mode means that the CCLK2  signal is used as  the CPU clock;
the 2X clock  mode means that the PCLK signal  (half the frequency and
the phase indicator  of CCLK2) is used as the  CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while  the rest of the system  runs at the frequency  of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface  is converted by the SL82C465 automatically
to  satisfy  the requirement  of  individual  clocks.  Table 1-1  [see
datasheet] lists  the operating frequencies  of the CPU local  bus and
the system logic with the oscillator used.

The 2X  clock mode is recommended  for a CPU frequency  no faster than
33Mhz because the system logic  is available at the targeted speed and
the  performance  is  slightly  better  than if  1X  clock  mode  were
used. For  a CPU  frequency faster  than 33Mhz, the  1X clock  mode is
preferred  for  486  systems  because  it  becomes  increasingly  more
difficult to  build a reliable  system with an oscillator  faster than
66Mhz.

***Versions:...
***Features:...
*TI (Texas Instruments)...
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