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**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
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**SL82C360 'Haydn' 80386DX/SX chipset [no datasheet] c:Jun91
***Notes:...
***Configurations:...
**SL82C460 'Haydn II' 80486 chipset [no datasheet] c:Jun91...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91...
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91
***Info:
The SL82C365 supports direct-mapped cache system with data size ranged
from 16KB to 1MB and line size ranged from 1 to 4 doublewords.
Without any external logic, SL82C365 supports 1 to 4 banks of cache
SRAMs independent of the line size. An 8-bit tag comparator is
integrated into the chip which not only saves on the system cost but
also improves the overall performance. 25ns tag SRAM and 35ns data
SRAM are adequate for zero wait state non-pipelined 33Mhz
operation. Assuming 8Kx8, 16Kx4, 32Kx8 and 64Kx4 SRAMs are used for
tag SRAM, the selectable organization is indicated in Table 1-1. [see
datasheet] More options are available for data RAM configurations
because of the flexibility in selecting the number of banks. Refer to
section 1.13 [see datasheet] for detailed design examples.
***Versions:...
***Features:...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
**UM8890 Pentium chipset [no datasheet] ?
***Notes:...
***Configurations:...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
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*ZyMOS...
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