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**Quote style:
To avoid  thousands of quote marks  and colliding with quote  marks in
the  text, I  have used  a modified  quotation style.   Anything in  a
section  titled "Info:"  or "Features:"  is a  quote from  a datasheet
unless otherwised stated in that  section.  In these sections anything
inside  [] is  an  annotation and  not part  of  the datasheet  unless
otherwise stated in that section.

Under any other section, the text is my own unless indicated with "".

Also  this document  does not  contain the  entire datasheet  for each
chip, usually only the first few pages are included to give an outline
of it. Some datasheets are 100s of pages other are only 1.

**Cant find a chip?...
**Why this document is not GPL or a wiki...
**Definition of a chip set:...
**'chip set', 'chip-set' or 'chipset'?...
**What's not included:...
**Who made the first chip set?...
**Spelling errors/mistyped words...
**Info needed on:...
**A note on VESA support of 486 chipsets....
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95
***Info:...
***Configurations:...
***Features:...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96
***Info:...
***Configurations:...
***Features:
o   Supports Intel Pentium CPU and other compatible CPU at 
    66/60/50MHz (external clock speed)
o   Supports VGA Shared Memory Architecture
    - Direct Memory Accesses
    - Shared Memory Area 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M, 4M.
    - Built-in 2-Priority Scheme.
o   Supports the Pipelined Address Mode of Pentium CPU.
o   Integrated Second Level (L2) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Supports Pipelined Burst SRAM.
    - Supports 256 KBytes to 1 MBytes Cache Sizes.
    - Cache Read/Write Cycle of 3-1-1-1 Pipelined Burst SRAM at 66 
      Mhz and 3-1-1-1-1-1-1-1 at back to back read cycle.
o   Integrated DRAM Controller
    - Supports 4 RAS lines, the memory size is from 4MBytes up to 
      512Mbytes.
    - Supports 256K/512K/1M/2M/4M/16M x N 70ns FP/EDO DRAM
    - Supports 4K Refresh DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports 32 bits/64 bits mixed mode configuration
    - Supports Concurrent Write Back
    - Table-free DRAM Configuration, Auto-detect DRAM size, Bank 
      Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
    - Supports CAS before RAS "Intelligent Refresh"
    - Supports Relocation of System Management Memory
    - Programmable CAS# Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KByte to 1 Mbyte)
o   Supports EDO/FP 5/6-2-2-2/-3-3-3 Burst Read Cycles
o   Two Programmable Non-Cacheable Regions
o   Option to Disable Local Memory in Non-Cacheable Regions
o   Shadow RAM in Increments of 16 KBytes
o   Supports SMM Mode of CPU.
o   Supports CPU Stop Clock.
o   Supports Break Switch.
o   Provides High Performance PCI Arbiter.
    - Supports 4 PCI Master.
    - Supports Rotating Priority Mechanism.
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated PCI Bridge
    - Supports Asynchronous PCI Clock.
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles.
    - Zero Wait State Burst Cycles.
    - Supports Advance Snooping for PCI Master Bursting.
    - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o   388-Pin BGA Package.
o   0.5μm CMOS Technology.

**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...