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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95
***Info:...
***Configurations:...
***Features:
****5501 PCI/ISA Cache Memory Controller (PCMC) 
o   Supports the 510\60, 567\66, 735\90, 815\100 MHz and 75 MHz 
    Pentium Processor
o   Supports M1 and Other Pentium Compatible CPU 
o   Supports the Pipelined Address Mode of the Pentium or the P54C
    Processor 
o   Integrated Second Level (L2) Cache Controller 
    - Write Through and Write Back Cache Modes 
    - 8 bits or 7 bits Tag with Direct Mapped Organization 
    - Supports Standard and Burst SRAMs 
    - Supports 64 KBytes to 2 MBytes Cache Sizes 
    - Cache Read/Write Cycle of 3-2-2-2 or 4-2-2-2 Using Standard 
      SRAMs at 66 MHz 
    - Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz 
o   Integrated DRAM Controller 
    - Supports 8 Banks of SIMMs up to 512 MBytes of Cacheable Main 
      Memory 
    - Supports "Table-Free" DRAM Configuration 
    - Concurrent Write Back 
    - CAS#-before-RAS# Transparent DRAM Refresh 
    - Supports 256K/512K/1M/2M/4M/16M xN 70ns Fast Page Mode and EDO 
      DRAM 
    - The Fastest Burst Cycle Speed for FP and EDO are 6-3-3-3 and 
      6-2-2-2 respectively 
    - Programmable CAS# driving Current
    - Programmable DRAM Speed 
o   Two Programmable Non-Cacheable Regions
o   Option to Disable Local Memory in Non-Cacheable Regions 
o   Shadow RAM in Increments of 16 KBytes
o   Supports Pentium/P54C SMM Mode
o   Supports CPU Stop Clock
o   Provides High Performance PCI Arbiter
    - Supports Four PCI Masters
    - Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead
o   Integrated PCI Bridge
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles
    - PCI Burst Write in the Pace of  X-2-2-2-....
    - PCI Burst Read L2 Cache in X-2-2-2-....
    - PCI Burst Read DRAM in X-3-2-3-2-....
    - Cache Snoop Filters Ensure Data Coherency and Minimize Snoop 
      Frequency
    - Meet PCI Specification Buffer Strength
o   208-Pin PQFP Package
o   0.6μm CMOS Technology

****5502 PCI Local Data Buffer (PLDB) ...
****5503 PCI System I/O (PSIO)...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
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*Unresearched:...
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*Winbond...
*ZyMOS...
*General Sources:...