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**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HTK340 "Shasta" 486 Chip Set c:Jun92
***Notes:
Date based on datasheet of HT44
***Info:
The HTK340 chip set is a two chip, high performance, cost-effective
solution for the 80486SX DX, and DX2 processing environments. In its
minimum configuration, this highly integrated chip set requires only
four external TTL devices to implement a fully compatible IBM PC/AT
system at speeds up to 33MHZ.
The HTK340 is based upon Headland's HTK320 Bus Architecture and
consists of the HT321-ISA Bus Controller and the HT342-Memory Control
Unit (MCU). Both chips are packaged in 184 pin plastic quad flat
packs.
The HTK340 is unique in that it provides performance approximating
that of large secondary cache systems, including the highest
performance write back cache architectures, without any external
cache. Secondary cache solutions should be considered in applications
that make use of multi-tasking and large model operating systems. The
Headland HT44 secondary cache was designed to meet the cost and
performance objectives for these applications. The key to this level
of performance is the 4-level deep write buffer, which includes byte
gathering for up to 32-bit DRAM writes.
Due to the effectiveness of the primary cache internal to the 80486
most of the bus activity in a PC/AT compatible environment consists of
writes. Indeed, this write activity consists almost exclusively of
writes of either bytes or Words (16 bit entities). In addition, much
of this write activity is into sequential memory locations. The byte
gathering feature of the buffer has the effect of reducing the number
of memory accesses required. Since the 80486 can always write into the
buffer with zero wait states (assuming the buffer is not full), and
the buffer can empty faster than it can be filled for most write
activity, the net effect is that the writes from the CPU never cause a
wait state.
The HTK340 can support Peripheral Devices such as VGA or SCSI on the
local processor bus, or any other devices that are designed to work
within the 80486 bus protocol and timing. By eliminating the ISA
backplane bottleneck, system designers can greatly improve the
performance of functions such as graphics generation and disk access.
The HTK340 supports up to 4 banks of DRAM, configurable as 1-4
banks. This flexible memory architecture allows for any memory type,
from 256K to 16M devices, in any bank. Maximum system performance is
achieved from the DRAM banks through various means, including
interleaving of memory banks and/or paging, and CAS before RAS
refresh. The memory can also be tuned to maximum potential through the
use of extensive DRAM timing control registers. These controls
include: precharge time, access time on reads, active time on writes,
as well as CAS and RAS delays. In addition, further system perfor-
mance is gained by separate timing parameters on the read and write
cycles which allow system designers to take maximum advantage of the
pipelined structure of the chip set.
The HTK340 also supports extensive mapping registers, which allow
system designers to take maximum advantage of system memory. The chip
set supports Shadow/Remap in 16K blocks between the 640K and 1M
boundaries, and eliminates the requirement for external decoding logic
by supporting 26 programmable non-cache regions. Devices which meet
HTK340 local bus requirements may be implemented without external
TTL. The mapping structure of the HTK340 provides for a single 8-bit
EPROM to be used for both the System and Video BIOS, further reducing
system chip count and cost.
***Configurations:...
***Features:...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
**Later Chipsets:
Info sourced from the very useful plasma-online.de:
http://www.plasma-online.de/index.html?content=http%3A//www.plasma-online.de/english/identify/picture/pcchips.html
Chipset name | OEM of | used on mainboard
---------------+---------------------------+-----------------------------------------
HX Pro | ALi M1521/M1523 |
SX Pro | SiS 530/5595 | M598
AGP Pro PC-100 | VIA VT82C598AT/VT82C596B | M577
TX AGP Pro | SiS 5591/5595/6326 |
TX Two | ALi M1531/M1543 |
TX Pro | ALi M1531/M1543 | M560, M575
TX Pro II | SiS 5597/5598 | M571
TX Pro III | VIA VT82C580VPX/VT82C586B | M573
TX Pro IV | SiS 5591/5592 | M570
Top Gun | ALi Aladdin IV+ | M565
VIA GRA | VIA VT8501/VT82C596B | M858LMR
VX Pro | VIA VT82C580VP/VT82C586B |
VX Pro + | VIA VT82C580VPX/VT82C586B |
VX Pro II | UTron / HiNT UT801X |
VX two | VIA VT82C580VP/VT82C586B | Amptron PM-8600A
VX two | VIA VT82C580VPX/VT82C586B | Amptron PM-8600B
BXToo | VIA Apollo Pro | M760V, M761V
BXToo | VIA VT82C693/VT82C686A | M767V
BXPro | SiS 600/5595 | M747
BXCel | ALi M1621/M1543 | M726, M729
BXpert | VIA VT82C691/VT82C596 |
BXTel | VIA Apollo Pro | M730
Xcel 2000 | SiS 620/5595 | M741LMRT
Super TX | SiS 5597/5598 | ASUS SP97-V, SP98-N, Jetway J-TX98R2
Super TX | ALi M1531/M1543 |
Super TX | ALi M1541/M1543 | Biostar M5ALA, M5ALC, Pionex MBD-P5ABx
Super TX3 | SiS 5571 |
Super TX4 AGP | |
GFXcel | SiS 630 |
GFXpro | ALi M1631/M1535D |
T-Bird | SiS730S | M810
---------------+---------------------------+----------------------------------------
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*Unresearched:...
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