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*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
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*OPTi...
**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94
***Notes:...
***Info:...
***Versions:...
***Features:
o   Fully compliant to the PCI V2.0 Specification 
o   Up to four PCI masters 
o   Supports system operational speeds of 25, 33, 40, and 50MHz 
o   Provides central arbiter to arbitrate the bus requests between: 
    - host CPU 
    - PCI masters 
    - DMA/ISA masters 
    - Refresh 
o   Offers programmable priority scheme for both the central arbiter 
    and DMA channels: 
    - Fixed 
    - Rotating 
    - Fixed/Rotating combination 
o   Burst mode PCI accesses to local memory support 
o   Combine host CPU sequential writes into PCI burst write cycles 
o   Interfaces with all OPTi's VL chipset solutions 
o   Single 208-pin PQFP (Plastic Quad Flat Pack) 


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