[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D 
    - AMD 486DX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct Mapped Cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page-hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
    - Programmable wait states for DRAM reads and writes
    - Enhanced DRAM configuration map
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
    - Programmable wake-up events through hardware, software and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
    - One programmable GREEN event timer
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
    - Integrates DMA, timer and interrupt controllers
    - Optional PS/2 style IRQ1 and 12 latching
o   VESA VL interface:
    - Conforms to the VESA v2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high-speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C898         System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C360   'Haydn' 80386DX/SX chipset [no datasheet]         c:Jun91
***Notes:...
***Configurations:...
**SL82C460   'Haydn II' 80486 chipset   [no datasheet]         c:Jun91...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...